参数资料
型号: SL28647CLCT
厂商: SILICON LABORATORIES
元件分类: 时钟产生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72
封装: 10 X 10 MM, ROHS COMPLIANT, QFN-72
文件页数: 8/27页
文件大小: 269K
代理商: SL28647CLCT
SL28647
.....................Document #: 001-05103 Rev *B Page 16 of 27
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs and SRC
outputs if they are set to be stoppable in SMbus while the rest
of the clock generator continues to function. The set-up time
for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 9.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running. All stopped PCI outputs are
driven Low, SRC outputs are High/Low if set to driven and
Low/Low if set to tri-state.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
DOT96C
DOT96T
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
PD
1.8mS
CPU_STOP#
Figure 8. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 9. PCI_STP# Assertion Waveform
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running
CPUT(Free Running
PD
1.8 ms
CPU_STOP#
Figure 10. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
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