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参数资料
| 型号： | SM320C30HFGM50 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 50 MHz, OTHER DSP, CQFP196 |
| 封装： | NONCONDUCTIVE TIE BAR, CERAMIC, QFP-196 |
| 文件页数： | 9/48页 |
| 文件大小： | 874K |
| 代理商： | SM320C30HFGM50 |
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SMJ320C30
DIGITAL SIGNAL PROCESSOR
SGUS014H -- FEBRUARY 1991 -- REVISED JUNE 2004
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
memory read/write timing
The following table defines memory read/write timing parameters for (M)STRB.
timing parameters for a memory [(M)STRB = 0] read/write (see Figure 10 and Figure 11)
NO
320C30-40
320C30-50
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
11
td[H1L-(M)SL]
Delay time, H1 low to (M)STRB low
0*
10
0*
4
ns
12
td[H1L-(M)SH]
Delay time, H1 low to (M)STRB high
0*
6
0*
4
ns
13.1
td(H1H-RWL)
Delay time, H1 high to R/W low
0*
9
0*
7
ns
13.2
td[H1H-(X)RWL]
Delay time, H1 high to (X)R/W low
0*
13
0*
11
ns
14.1
td(H1L-A)
Delay time, H1 low to A valid
0*
11
0*
9
ns
14.2
td[H1L-(X)A]
Delay time, H1 low to (X)A valid
0*
9
0*
8
ns
15.1
tsu(D-H1L)R
Setup time, D valid before H1 low (read)
14
10
ns
15.2
tsu[(X)DR-H1L]R
Setup time, (X)D before H1 low (read)
16
14
ns
16
th[H1L-(X)D]R
Hold time, (X)D after H1 low (read)
0*
ns
17.1
tsu(RDY-H1H)
Setup time, RDY before H1 high
8
6
ns
17.2
tsu[(X)RDY-H1H]
Setup time, (X)RDY before H1 high
9
8
ns
18
th[H1H-(X)RDY]
Hold time, (X)RDY after H1 high
0
ns
19
td[H1H-(X)RWH]W
Delay time, H1 high to (X)R/W high (write)
9
7
ns
20
tv[H1L(X)D]W
Valid time, (X)D after H1 low (write)
17
14
ns
21
th[H1H-(X)D]W
Hold time, (X)D after H1 high (write)
0*
ns
22.1
td(H1H-A)
Delay time, H1 high to A valid on back-to-back write cycles (write)
15
12
ns
22.2
td[H1H-(X)A]
Delay time, H1 high to (X)A valid on back-to-back write cycles (write)
21
18
ns
26
td[A-(X)RDY]
Delay time, (X)RDY from A valid
7*
6*
ns
Numbers in this column match those used in Figure 10 and Figure 11.
* This parameter is not production tested.
相关PDF资料 |
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相关代理商/技术参数 |
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| SM320C31GFAS60 | 制造商:Texas Instruments 功能描述:3RD GENERATION DSP, 60 MHZ - Trays |
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