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参数资料
| 型号： | SM320C6203W16 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮点数字信号处理器 |
| 文件页数： | 25/64页 |
| 文件大小： | 939K |
| 代理商： | SM320C6203W16 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
clock PLL (continued)
Table 4.
’
C6701 PLL Component Selection Table
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHz)
50
–
167
CLKOUT2
RANGE
(MHz)
R1
(
)
C1
(nF)
C2
(pF)
TYPICAL
LOCK TIME
(
μ
s)
x4
12.5
–
41.7
25
–
83.5
60.4
27
560
75
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
Available Multiply Factors
CLKMODE1
CLKMODE0
PLL Multiply
Factors
CPU Clock
Frequency
f(CPUCLOCK)
1 x f(CLKIN)
Reserved
Reserved
4 x f(CLKIN)
0
0
1
1
0
1
0
1
x1(BYPASS)
Reserved
Reserved
x4
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the
’
C6000 device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
CLKMODE0
CLKMODE1
PLL
PLLV
CLKIN
LOOP FILTER
PLLCLK
PLLMULT
CLKIN
P
C2
Internal to
’
C6701
CPU
CLOCK
C1
R1
3.3V
10 F
0.1 F
P
E
C3
C4
1
0
(see Table 3)
PLLFREQ1
PLLFREQ2
PLLFREQ3
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