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参数资料
| 型号： | SM320C6203W16 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮点数字信号处理器 |
| 文件页数： | 32/64页 |
| 文件大小： | 939K |
| 代理商： | SM320C6203W16 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles
(see Figure 12 and Figure 13)
NO.
’
C6701-14
’
C6701-16
UNIT
MIN
4.8
MAX
6
tsu(EDV-CKO1H)
th(CKO1H-EDV)
tsu(ARDY-CKO1H)
th(CKO1H-ARDY)
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Setup time, read EDx valid before CLKOUT1 high
ns
7
Hold time, read EDx valid after CLKOUT1 high
1.5
ns
10
Setup time, ARDY valid before CLKOUT1 high
3.5
ns
11
Hold time, ARDY valid after CLKOUT1 high
1.5
ns
switching characteristics for asynchronous memory cycles
(see Figure 12 and Figure 13)
NO.
PARAMETER
’
C6701-14
’
C6701-16
UNIT
MIN
MAX
1
td(CKO1H-CEV)
td(CKO1H-BEV)
td(CKO1H-BEIV)
td(CKO1H-EAV)
td(CKO1H-EAIV)
td(CKO1H-AOEV)
td(CKO1H-AREV)
td(CKO1H-EDV)
td(CKO1H-EDIV)
td(CKO1H-AWEV)
Delay time, CLKOUT1 high to CEx valid
–
1.0
4.5
ns
2
Delay time, CLKOUT1 high to BEx valid
4.5
ns
3
Delay time, CLKOUT1 high to BEx invalid
–
1.0
ns
4
Delay time, CLKOUT1 high to EAx valid
4.5
ns
5
Delay time, CLKOUT1 high to EAx invalid
–
1.0
ns
8
Delay time, CLKOUT1 high to AOE valid
–
1.0
4.5
ns
9
Delay time, CLKOUT1 high to ARE valid
–
1.0
4.5
ns
12
Delay time, CLKOUT1 high to EDx valid
4.5
ns
13
Delay time, CLKOUT1 high to EDx invalid
–
1.0
ns
14
Delay time, CLKOUT1 high to AWE valid
–
1.0
4.5
ns
The minimum delay is also the minimum output hold after CLKOUT1 high.
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