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参数资料
| 型号： | SM320C6701GLPS14 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 140 MHz, OTHER DSP, CBGA429 |
| 封装： | CERAMIC, BGA-429 |
| 文件页数： | 37/62页 |
| 文件大小： | 873K |
| 代理商： | SM320C6701GLPS14 |
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SMJ320C6701
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS030A – APRIL 2000 – REVISED APRIL 2001
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOLD/HOLDA TIMING
timing requirements for the hold/hold acknowledge cycles (see Figure 24)
NO.
’C6701-14
’C6701-16
UNIT
NO.
MIN
MAX
UNIT
1
tsu(HOLDH-CKO1H)
Setup time, HOLD high before CLKOUT1 high
5
ns
2
th(CKO1H-HOLDL)
Hold time, HOLD low after CLKOUT1 high
2
ns
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
switching characteristics for the hold/hold acknowledge cycles (see Figure 24)
NO.
PARAMETER
’C6701-14
’C6701-16
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
3
tR(HOLDL-EMHZ)
Response time, HOLD low to EMIF high impedance
4P
§
ns
4
tR(EMHZ-HOLDAL)
Response time, EMIF high impedance to HOLDA low
2P
ns
5
tR(HOLDH-HOLDAH)
Response time, HOLD high to HOLDA high
4P
7P
ns
6
td(CKO1H-HOLDAL)
Delay time, CLKOUT1 high to HOLDA valid
1
8
ns
7
td(CKO1H-BHZ)
Delay time, CLKOUT1 high to EMIF Bus high impedance
*1
*8
ns
8
td(CKO1H-BLZ)
Delay time, CLKOUT1 high to EMIF Bus low impedance
*1
*12
ns
9
tR(HOLDH-BLZ)
Response time, HOLD high to EMIF Bus low impedance
3P
6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
*This parameter is not tested.
DSP Owns Bus
External Requester
DSP Owns Bus
’C6701
Ext Req
’C6701
8
7
3
4
6
1
2
CLKOUT1
HOLD
HOLDA
EMIF Bus
1
5
9
2
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320C6701GLPS16 | 制造商:Texas Instruments 功能描述:DSP,1000 MFLOPS,167MHZ,-40C/+90C,C-BGA - Trays |
| SM320C6701GLPW14 | 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 140MHz 1120MIPS 429-Pin CFCBGA Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TISSM320C6701GLPW14 FLOATING POINT DSP |
| SM320C6701S14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701S16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6701W14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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