参数资料
型号: SM320F28335GHHAEP
厂商: Texas Instruments
文件页数: 103/167页
文件大小: 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
产品培训模块: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
标准包装: 189
系列: TMS320F28x3x Delfino™, C2000™
核心处理器: C28x
芯体尺寸: 32-位
速度: 150MHz
连通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外围设备: DMA,POR,PWM,WDT
输入/输出数: 88
程序存储器容量: 512KB(256K x 16)
程序存储器类型: 闪存
RAM 容量: 34K x 16
电压 - 电源 (Vcc/Vdd): 1.805 V ~ 1.995 V
数据转换器: A/D 16x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 179-LFBGA
包装: 托盘
产品目录页面: 718 (CN2011-ZH PDF)
其它名称: 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
3.2.12 External Interrupts (XINT1-XINT7, XNMI)
The devices support eight masked external interrupts (XINT1-XINT7, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). XINT1,
XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts
can accept inputs from GPIO0 – GPIO31 pins. XINT3 – XINT7 interrupts can accept inputs from
GPIO32 – GPIO63 pins.
3.2.13 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.14 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.
3.2.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
and the ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
3.2.16 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and
places it in the lowest possible power consumption mode. A reset or external signal
can wake the device from this mode.
40
Functional Overview
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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