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参数资料
| 型号： | SM79108L25 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded |
| 中文描述： | 8位微控制器与8KB闪存 |
| 文件页数： | 12/26页 |
| 文件大小： | 590K |
| 代理商： | SM79108L25 |
January 2003
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/26
Preliminary Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc. SM79108
Preliminary
6. Analog-to-Digital Converter (ADC)
The SM79108 equips with 4-channels, 8-bit ADC which is available at P3.4~P3.7. S/W can select one of the 4 ADC chan-
nels by setting SFR ADC Status and Control Register (ADSCR, 8EH) bit CH0~CH1. The ADC can do single conversion or
continuously conversion. When the conversion is completed, ADC puts the result in the ADC Data Register (ADCD, 8FH)
and sets COM bit of ADSCR (ADSCR.7). After channel selection bit CH[1:0] of ADSCR and P3CON been set, the selected
pin of P3.4~P3.7 will function as ADC input pin instead of general purpose I/O pin which is due to priority of ADC function is
higher than I/O function. The rest of the P3.4~P3.7 pin will still function as general purpose I/O pin. Writes to the port register
will have no affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the
value in the port which is been read.
6.1 Straight line conversion
The ADC conversion relationship of input analog signal to digital output value is a linear straight line conversion relationship.
It will convert input signal in +Vdd V or above to 0FFH (full scale) and convert input signal +0V or below to 00H. The +Vdd is
the voltage applied to the IC.
6.2 ADC input clock frequency range
ADC input clock frequency range = 500KHz ~ 2.5MHz. User need to be aware of this frequency range limitation when using
ADC function. The frequency range limitation was induced by the sample-and-hold and DAC converter circuits inside of the
ADC submodule. If the ADC input clock frequency resides outside of the range then ADC function may not work.
ADC input clock frequency = oscillator frequency / divider. Divider elected by ADCSS[1:0] setting of ADSCR
One conversion time = 20 ADC clock cycles / ADC input clock frequency
Maximum sample rate of ADC = ADC input clock frequency / 20
6.3 ADC registers - ADSCR, ADR
ADC Registers - ADSCR, 8EH)
COM: ADC conversion complete bit. This bit is a read only bit which is set each time conversion is completed. It is
cleared whenever ADSCR is written or ADCD is read. Reset clears this bit.
COM = 1 means conversion completed
COM = 0 means conversion not completed
CON: ADC continuous conversion bit. When set, the ADC will convert samples continuously and update the ADCD
register at the end of each conversion. When reset, only one conversion is allowed. Reset clears this bit.
CON = 1 means continuous mode
CON = 0 means signal mode
bit-7
COM
R
0
bit-0
R
-
*
CON
R/W
0
ADCSS1
R/W
0
ADCSS0
R/W
0
CH1
R/W
0
CH0
R/W
0
R
-
*
Read /Write:
Reset value:
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