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参数资料
| 型号： | SM79108L25 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Micro-controller with 8KB flash & 256 Bytes RAM embedded |
| 中文描述： | 8位微控制器与8KB闪存 |
| 文件页数： | 14/26页 |
| 文件大小： | 590K |
| 代理商： | SM79108L25 |
January 2003
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/26
Preliminary Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc. SM79108
Preliminary
Unused
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*
Set ADCE1
ADCE1
Set ADCE0
ADCE0
User may compare bits ADCE[3:0] of P3CON with bits CH[1:0] of ADSCR. User may consider P3CON as register for dis-
tinguish general purpose I/O function from other specific functions. After bit ADCE[3:0] been set, the corresponding I/O pin
will be assigned as high impedance input pins for signal input. On the other hand, the setting of CH[1:0] will select ADC
channels accordingly.
= 1 enables the ADC function on pin P3.5/A13/ADC1,
= 0 disables the ADC function on pin P3.5/A13/ADC1,
= 1 enables the ADC function on pin P3.4/A12/ADC0,
= 0 disables the ADC function on pin P3.4/A12/ADC0,
6.4 ADC Interrupt
The ADC module will generate one interrupt once one analog-to-digital conversion is completed. The ADC interrupt vector
locates at 4BH. There are three SFRs for configuring ADC interrupt: IP1, IE1 and IFR. To use ADC interrupt is the same
as to use other generic 8052 interrupts. That means using EADC of IE1 for enable/disable ADC interrupt, using PADC for
assign ADC interrupt priority. Whenever ADC interrupt occurs, ADCIF will be set to 1. After ADC interrupt subroutine (vec-
tor) been executed, ADCIF will be cleared to 0.
I
nterrupt Priority I Register (IP1, 0B9H
)
Interrupt priority bit PADC = 1 assigns high interrupt priority of ADC interrupt
Interrupt priority bit PADC = 0 assigns low interrupt priority of ADC interrupt
Interrupt Enable I Register (IE1, 0A9H)
Interrupt enable bit EADC = 1 enables the ADC interrupt
Interrupt priority bit EADC = 0 disables the ADC interrupt
Interrupt Flag Register (IFR, 0AAH)
Interrupt flag bit ADCIF will be set to 1 when ADC interrupt occurs. Interrupt flag bit ADCIF will be clear to 0 if ADC
Interrupt subroutine executed.
bit-7
Unused
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*
bit-0
Unused
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*
Unused
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*
Unused
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*
Unused
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*
PADC
R/W
0
Unused
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*
Unused
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*
Read /Write:
Reset value:
bit-7
Unused
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*
bit-0
Unused
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*
Unused
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*
Unused
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*
Unused
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*
EADC
R/W
0
Unused
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*
Unused
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*
Read /Write:
Reset value:
bit-7
bit-0
Unused
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*
Unused
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*
Unused
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*
Unused
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*
ADCIF
R/W
0
Unused
-
*
Unused
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*
Read /Write:
Reset value:
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