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参数资料
| 型号： | SMJ320C6201BS16 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮点数字信号处理器 |
| 文件页数： | 34/64页 |
| 文件大小： | 939K |
| 代理商： | SMJ320C6201BS16 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 14)
NO.
’
C6701-14
MIN
’
C6701-16
MIN
UNIT
MAX
MAX
7
tsu(EDV-SSCLKH)
th(SSCLKH-EDV)
Setup time, read EDx valid before SSCLK high
2.6
2.5
ns
8
Hold time, read EDx valid after SSCLK high
1.5
1.5
ns
switching characteristics for synchronous-burst SRAM cycles
(full-rate SSCLK)
(see Figure 14 and Figure 15)
NO.
PARAMETER
’
C6701-14
MIN
’
C6701-16
MIN
UNIT
MAX
MAX
1
tosu(CEV-SSCLKH)
toh(SSCLKH-CEV)
tosu(BEV-SSCLKH)
toh(SSCLKH-BEIV)
tosu(EAV-SSCLKH)
toh(SSCLKH-EAIV)
tosu(ADSV-SSCLKH)
toh(SSCLKH-ADSV)
tosu(OEV-SSCLKH)
toh(SSCLKH-OEV)
tosu(EDV-SSCLKH)
toh(SSCLKH-EDIV)
tosu(WEV-SSCLKH)
toh(SSCLKH-WEV)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
Output setup time, CEx valid before SSCLK high
0.5P
–
1.5
0.5P
–
1.3
ns
2
Output hold time, CEx valid after SSCLK high
0.5P
–
2.5
0.5P
–
2.3
ns
3
Output setup time, BEx valid before SSCLK high
0.5P
–
1.6
0.5P
–
1.6
ns
4
Output hold time, BEx invalid after SSCLK high
0.5P
–
2.5
0.5P
–
2.3
ns
5
Output setup time, EAx valid before SSCLK high
0.5P
–
1.7
0.5P
–
1.7
ns
6
Output hold time, EAx invalid after SSCLK high
0.5P
–
2.5
0.5P
–
2.5
ns
9
Output setup time, SSADS valid before SSCLK high
0.5P
–
1.5
0.5P
–
1.3
ns
10
Output hold time, SSADS valid after SSCLK high
0.5P
–
2.5
0.5P
–
2.3
ns
11
Output setup time, SSOE valid before SSCLK high
0.5P
–
1.5
0.5P
–
1.3
ns
12
Output hold time, SSOE valid after SSCLK high
0.5P
–
2.5
0.5P
–
2.5
ns
13
Output setup time, EDx valid before SSCLK high
0.5P
–
1.5
0.5P
–
1.3
ns
14
Output hold time, EDx invalid after SSCLK high
0.5P
–
2.5
0.5P
–
2.5
ns
15
Output setup time, SSWE valid before SSCLK high
0.5P
–
1.5
0.5P
–
1.3
ns
16
Output hold time, SSWE valid after SSCLK high
0.5P
–
2.5
0.5P
–
2.3
ns
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|---|---|
| SMJ320C6201BW14 | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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相关代理商/技术参数 |
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|---|---|
| SMJ320C6201BW14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6201BW16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SMJ320C6203 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PORCESSOR |
| SMJ320C6203_08 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PORCESSOR |
| SMJ320C6203GLPM20 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED POINT SIGNAL PROCESSOR |
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