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参数资料
| 型号： | SMJ320C6201BW16 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 浮点数字信号处理器 |
| 文件页数： | 38/64页 |
| 文件大小： | 939K |
| 代理商： | SMJ320C6201BW16 |
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SGUS030B
–
APRIL 2000
–
REVISED MAY 2001
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 18)
NO.
’
C6701-14
MIN
’
C6701-16
MIN
UNIT
MAX
MAX
7
tsu(EDV-SDCLKH)
th(SDCLKH-EDV)
Setup time, read EDx valid before SDCLK high
2
2
ns
8
Hold time, read EDx valid after SDCLK high
3
3
ns
switching characteristics for synchronous DRAM cycles
(see Figure 18
–
Figure 23)
NO.
PARAMETER
’
C6701-14
MIN
’
C6701-16
MIN
UNIT
MAX
MAX
1
tosu(CEV-SDCLKH)
toh(SDCLKH-CEV)
tosu(BEV-SDCLKH)
toh(SDCLKH-BEIV)
tosu(EAV-SDCLKH)
toh(SDCLKH-EAIV)
Output setup time, CEx valid before SDCLK high
1.5P
–
5
1.5P
–
4
ns
2
Output hold time, CEx valid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
3
Output setup time, BEx valid before SDCLK high
1.5P
–
5
1.5P
–
4
ns
4
Output hold time, BEx invalid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
5
Output setup time, EAx valid before SDCLK high
1.5P
–
5
1.5P
–
4
ns
6
Output hold time, EAx invalid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
9
tosu(SDCAS-SDCLKH)
Output setup time, SDCAS valid before SDCLK
high
1.5P
–
5
1.5P
–
4
ns
10
toh(SDCLKH-SDCAS)
tosu(EDV-SDCLKH)
toh(SDCLKH-EDIV)
Output hold time, SDCAS valid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
11
Output setup time, EDx valid before SDCLK high
1.5P
–
5
1.5P
–
4
ns
12
Output hold time, EDx invalid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
13
tosu(SDWE-SDCLKH)
Output setup time, SDWE valid before SDCLK
high
1.5P
–
5
1.5P
–
4
ns
14
toh(SDCLKH-SDWE)
Output hold time, SDWE valid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
15
tosu(SDA10V-SDCLKH)
Output setup time, SDA10 valid before SDCLK
high
1.5P
–
5
1.5P
–
4
ns
16
toh(SDCLKH-SDA10IV)
Output hold time, SDA10 invalid after SDCLK
high
0.5P
–
1.9
0.5P
–
1.5
ns
17
tosu(SDRAS-SDCLKH)
Output setup time, SDRAS valid before SDCLK
high
1.5P
–
5
1.5P
–
4
ns
18
toh(SDCLKH-SDRAS)
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
Output hold time, SDRAS valid after SDCLK high
0.5P
–
1.9
0.5P
–
1.5
ns
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