参数资料
型号: SN54ACT74W
厂商: TEXAS INSTRUMENTS INC
元件分类: 锁存器
英文描述: ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14
封装: CERAMIC, DFP-14
文件页数: 5/9页
文件大小: 177K
代理商: SN54ACT74W
SN54ACT74, SN74ACT74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS520E – AUGUST 1995 – REVISED JANUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature (unless otherwise
noted) (see Figure 1)
FROM
TO
SN74ACT74
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
MAX
UNIT
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
fmax
145
210
125
MHz
tPLH
PRE or CLR
QorQ
3
5.5
9.5
2.5
10.5
ns
tPHL
PRE or CLR
Q or Q
3
6
10
3
11.5
ns
tPLH
CLK
QorQ
4
7.5
11
4
13
ns
tPHL
CLK
Q or Q
3.5
6
10
3
11.5
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
45
pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPLH
VOH
VOL
3 V
0 V
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
tPLH/tPHL
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤ 1 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
LOAD CIRCUIT
From Output
Under Test
CL = 50 pF
(see Note A)
S1
2
× VCC
500
500
Open
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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