参数资料
型号: SN54LS273J
厂商: ON SEMICONDUCTOR
元件分类: 锁存器
英文描述: LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20
封装: CERAMIC, DIP-20
文件页数: 1/3页
文件大小: 63K
代理商: SN54LS273J
5-1
FAST AND LS TTL DATA
OCTAL D FLIP-FLOP WITH CLEAR
The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of
eight D-Type Flip-Flops with a Common Clock and an asynchronous active
LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3
inch lead spacing.
8-Bit High Speed Register
Parallel Register
Common Clock and Master Reset
Input Clamp Diodes Limit High-Speed Termination Effects
18
17
16
15
14
13
12
3
4
5
6
7
20
19
8
VCC
MR
Q7
D7
D6
Q6
D5
Q5
D4
Q0
D0
D1
Q1
Q2
D2
D3
910
Q3 GND
12
11
Q4
CP
CONNECTION DIAGRAM DIP (TOP VIEW)
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP
Clock (Active HIGH Going Edge) Input
0.5 U.L.
0.25 U.L.
D0 –D7
Data Inputs
0.5 U.L.
0.25 U.L.
MR
Master Reset (Active LOW) Input
0.5 U.L.
0.25 U.L.
Q0 –Q7
Register Outputs (Note b)
10 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
TRUTH TABLE
MR
CP
Dx
Qx
L
X
L
H
L
H = HIGH Logic Level
L = LOW Logic Level
X = Immaterial
LOGIC DIAGRAM
CP
MR
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
CP D
CD Q
14
1
26
7
3
8
4
5
9
11
12
13
15
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
17
18
16
19
SN54/74LS273
OCTAL D FLIP-FLOP
WITH CLEAR
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
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