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参数资料
| 型号： | SN54LS273J |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 锁存器 |
| 英文描述： | LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20 |
| 封装： | CERAMIC, DIP-20 |
| 文件页数： | 3/3页 |
| 文件大小： | 63K |
| 代理商： | SN54LS273J |
5-3
FAST AND LS TTL DATA
SN54/74LS273
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sb l
P
Limits
Ui
T
C
di i
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tw
Pulse Width, Clock or Clear
20
ns
Figure 1
ts
Data Setup Time
20
ns
Figure 1
th
Hold Time
5.0
ns
Figure 1
trec
Recovery Time
25
ns
Figure 2
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
1.3 V
CP
D
Qn
ts(H)
th(H)
ts(L)
th(L)
1/f max
tPLH
tPHL
MR
CP
Qn
1.3 V
trec
tPHL
tPLH
tW
1.3 V
*
tW
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
AC WAVEFORMS
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
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