- 您现在的位置：买卖IC网 > PDF目录373461 > SN54LVTH182504AHV (Texas Instruments, Inc.) Octal 3-State Inverting Buffer/Line Driver/Line Receiver; Package: SOEIAJ-20; No of Pins: 20; Container: Rail; Qty per Container: 40 PDF资料下载
参数资料
| 型号： | SN54LVTH182504AHV |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | Octal 3-State Inverting Buffer/Line Driver/Line Receiver; Package: SOEIAJ-20; No of Pins: 20; Container: Rail; Qty per Container: 40 |
| 中文描述： | 的3.3V ABT生根粉扫描测试设备与20位通用总线收发器 |
| 文件页数： | 24/35页 |
| 文件大小： | 544K |
| 代理商： | SN54LVTH182504AHV |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing description
All test operations of the ’LVTH18504A and ’LVTH182504A are synchronous to the TCK signal. Data on the TDI,
TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and
normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as
shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge
to TCK.
A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states to perform one instruction-register scan and one
data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO is used
to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 details the
operation of the test circuitry during each TCK cycle.
Table 5. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
1
Test-Logic-Reset
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
2
Run-Test/Idle
3
Select-DR-Scan
4
Select-IR-Scan
5
Capture-IR
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
6
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
7–13
Shift-IR
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the instruction register scan
on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR
to Exit1-IR.
14
Exit1-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
15
Update-IR
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
16
Select-DR-Scan
17
Capture-DR
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
18
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP
on the rising edge of TCK as the TAP controller advances to the next state.
19–20
Shift-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
21
Exit1-DR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
22
Update-DR
In general, the selected data register is updated with the new data on the falling edge of TCK.
23
Select-DR-Scan
24
Select-IR-Scan
25
Test-Logic-Reset
Test operation completed.
相关PDF资料 |
PDF描述 |
|---|---|
| SN54LVTH18504AHV | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000 |
| SN54LVTH182504A | 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器)) |
| SN54LVTH18504A | 3.3-V ABT Scan Test Device With 20-Bit Universal Bus Transceivers(3.3VABT扫描测试装置(20位通用总线收发器)) |
| SN54LVTH182646AHV | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75 |
| SN54LVTH18646AHV | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN54S00J | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S00W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S02J | 制造商:Texas Instruments 功能描述: |
| SN54S03J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE (OC) - Rail/Tube |
| SN54S04J | 制造商:Texas Instruments 功能描述:Inverter 6-Element Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:INVERTER 6-ELEM BIPOLAR 14CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:HEX INVERTER *NIC* |
发布紧急采购，3分钟左右您将得到回复。