参数资料
型号: SN65LVDS122EVM
厂商: Texas Instruments, Inc.
英文描述: SN65LVDS122 Evaluation Module(SN65LVDS122评估模块)
中文描述: SN65LVDS122评估模块(SN65LVDS122评估模块)
文件页数: 20/22页
文件大小: 270K
代理商: SN65LVDS122EVM
Board Layout Patterns
3-4
Figure 3
5.Layer 3 Split V
CC
amd V
EE
Figure 3
6.Layer 4 GND Plane
Figure 3
7.PCB Fabrication Notes and Stackup
Single: Layer 1
GND: Layer 2
Split Power: Layer 3
GND: Layer 4
Stackup
0.006
0.042
0.006
Notes:
1) PWB to be fabricated to meet or exceed IPC-6012, Class 3 standards and workmanship conform to IPC-A-600,
Class 3 current revisions
2) Board material and construction to be UL approved and marked on the finished board.
3) Laminate materal: Copper-clad NELCO N4000-13 (DO NOT USE
13SI)
4) Copper weight: 1 oz finished
5) Finished thickness: 0.62
±
0.10
6) Minimum plating thickness in through holes: 0.001
7) SMOBC/HASL
8) LPI soldermask both sides using appropriate layer
artwork: color = green
9) LPI silkscreen as required: color = white
10)LPI soldermask both sides using appropriate layer
artwork: color = green
11)Minimum copper conductor width is: 0.010
Minimum conductor spacing is: 0.009
12)Number of finished layers: 4
13)Top layer 10 mil traces to be 50-
impedance
14)Spacing between layers 3 and 4 should be 0.006
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