参数资料
型号: SN65LVDS250_07
厂商: Texas Instruments, Inc.
英文描述: LVDS 4x4 CROSSPOINT SWITCH
中文描述: LVDS的4 × 4交叉点开关
文件页数: 6/18页
文件大小: 531K
代理商: SN65LVDS250_07
www.ti.com
OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
SN65LVDS250
SN65LVDT250
SLLS594B–MARCH 2004–REVISED OCTOBER 2004
PARAMETER
TEST CONDITIONS
MIN
247
-50
1.125
TYP
350
MAX
454
UNIT
mV
mV
V
|V
OD
|
|V
OD
|
V
OC(SS)
Differential output voltage magnitude
Change in differential output voltage magnitude between logic states
Steady-state common-mode output voltage
Change in steady-state common-mode output voltage between logic
states
Peak-to-peak common-mode output voltage
Supply current
Short-circuit output current
Differential short circuit output current
High-impedance output current
Differential output capacitance
See Figure 2
V
ID
=
±
100 mV
50
1.375
V
OC(SS)
See Figure 3
-50
50
mV
V
OC(PP)
I
CC
I
OS
I
OSD
I
OZ
C
O
50
150
145
27
12
±
1
mV
mA
mA
mA
μA
pF
R
L
=100
V
OY
or V
OZ
= 0 V
V
OD
= 0 V
V
O
= 0 V or V
CC
110
-27
-12
2
PARAMETER
TEST CONDITIONS
MIN
700
700
TYP
800
800
200
200
MAX
1200
1200
245
245
50
175
300
UNIT
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
sk(pp)
t
jit(per)
t
jit(cc)
t
jit(pp)
t
jit(det)
t
PHZ
t
PLZ
t
PZH
t
PZL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time (20%-80%)
Differential output signal fall time (20%-80%)
Pulse skew (|t
PHL
- t
PLH
|)
(1)
Channel-to-channel output skew
(2)
Part-to-part skew
(3)
Period jitter, rms (1 standard deviation)
(4)
Cycle-to-cycle jitter (peak)
(5)
Peak-to-peak jitteR
(6)
Deterministic jitter, peak-to-peak
(7)
Propagation delay, high-level-to-high-impedance output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance -to-high-level output
Propagation delay, high-impedance-to-low-level output
See Figure 4
ps
0
ps
ps
ps
ps
ps
ps
ps
See Figure 6
See Figure 6
See Figure 6
See Figure 6
1
8
3
17
110
65
60
48
6
6
See Figure 5
ns
300
300
(1)
(2)
(3)
t
sk(p)
is the magnitude of the time difference between the t
and t
of any output of a single device.
t
sk(o)
is the maximum delay time difference between drivers over temperature, V
, and process.
t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Input voltage = V
ID
= 200 mV, 50% duty cycle at 1.0 GHz, t
r
= t
f
= 50 ps (20% to 80%), measured over 1000 samples.
Input voltage = V
ID
= 200 mV, 50% duty cycle at 1.0 GHz, t
= t
f
= 50 ps (20% to 80%).
Input voltage = V
ID
= 200 mV, 2
23
-1 PRBS pattern at 2.0 Gbps, t
= t
= 50 ps (20% to 80%), measured over 200k samples.
Input voltage = V
ID
= 200 mV, 2
7
-1 PRBS pattern at 2.0 Gbps, t
r
= t
f
= 50 ps (20% to 80%).
(4)
(5)
(6)
(7)
6
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