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| 型号： | SN65LVDS94DGGR |
| 厂商： | Texas Instruments |
| 文件页数： | 1/17页 |
| 文件大小： | 0K |
| 描述： | IC LVDS SERDES RECEIVER 56-TSSOP |
| 标准包装： | 2,000 |
| 系列： | 65LVDS |
| 功能： | 串行器/解串器 |
| 输入类型： | LVDS |
| 输出类型： | LVTTL |
| 输入数： | 4 |
| 输出数： | 28 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 带卷 (TR) |
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FEATURES
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D22
D23
D24
GND
D25
D26
D27
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
CLKINM
CLKINP
A3M
A3P
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
D0
GND
VCC
D21
D20
D19
GND
D18
D17
D16
VCC
D15
D14
D13
GND
D12
D11
D10
VCC
D9
D8
D7
GND
D6
D5
D4
D3
VCC
D2
D1
DGG PACKAGE
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DESCRIPTION
SLLS298F – MAY 1998 – REVISED JANUARY 2006
LVDS SERDES RECEIVER
4:28 Data Channel Expansion at up to 1.904
Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
4 Data Channels and Clock Low-Voltage
Differential Channels in and 28 Data and
Clock Out Low-Voltage TTL Channels Out
Operates From a Single 3.3-V Supply and
250 mW (Typ)
5-V Tolerant SHTDN Input
Rising Clock Edge Triggered Outputs
Bus Pins Tolerate 4-kV HBM ESD
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
Consumes <1 mW When Disabled
Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
No External Components Required for PLL
Meets or Exceeds the Requirements of ANSI
EIA/TIA-644 Standard
Industrial Temperature Qualified
TA = -40°C to 85°C
Replacement for the DS90CR286
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift
registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended
LVTTL synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the
LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the
expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 1998–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN65LVDS94DGGRG4 | 功能描述:LVDS 接口集成电路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
| SN65LVDS95DGG | 功能描述:缓冲器和线路驱动器 Serdes Transmitter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SN65LVDS95DGG | 制造商:Texas Instruments 功能描述:Transceiver IC Transceiver Type:Eia/Tia- |
| SN65LVDS95DGGG4 | 功能描述:LVDS 接口集成电路 Serdes Transmitter RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
| SN65LVDS95DGGR | 功能描述:LVDS 接口集成电路 Serdes Transmitter RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
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