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| 型号： | SN65LVDS94DGGR |
| 厂商： | Texas Instruments |
| 文件页数： | 4/17页 |
| 文件大小： | 0K |
| 描述： | IC LVDS SERDES RECEIVER 56-TSSOP |
| 标准包装： | 2,000 |
| 系列： | 65LVDS |
| 功能： | 串行器/解串器 |
| 输入类型： | LVDS |
| 输出类型： | LVTTL |
| 输入数： | 4 |
| 输出数： | 28 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 带卷 (TR) |
www.ti.com
SN74FB2032
8
D0–D7
8
D8–D15
SN75LVDS93
LVDS
Interface
0 To 10 Meters
(Media Dependent)
TTL
Interface
W/Parity
16-Bit
BTL Bus
Interface
CLK
Backplane
Bus
8
D0–D7
8
D8–D15
CLK
Backplane
Bus
TTL
Interface
16-Bit
BTL Bus
Interface
XMIT Clock
RCV Clock
9 Bit Latchable
Transceiver/ With
Parity Generator
Parity
TTL
Interface
Parity
Error
TTL
Interface
W/Parity
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
SN74FB2032
9 Bit Latchable
Transceiver/ With
Parity Generator
9 Bit Latchable
Transceiver/ With
Parity Generator
SN75LVDS94
LOW COST VIRTUAL BACKPLANE TRANSCEIVER
Bus
Transceivers
LVDS Serdes
Transmitter
LVDS Serdes
Receiver
Bus
Transceivers
TTL
Inputs
Up To
21 or 28
Bits
LVDS
Serial Links
4 or 5
Pairs
TTL
Outputs
Up To
21 or 28
Bits
Bus
Transceivers
LVDS Serdes
Transmitter
LVDS Serdes
Receiver
Bus
Transceivers
Backplane
Bus
Backplane
Bus
SLLS298F – MAY 1998 – REVISED JANUARY 2006
APPLICATION INFORMATION (continued)
Figure 12. 16-Bit Bus Extension With Parity
Figure 13 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of a
VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem
serialized links.
Depending on the application, the designer will face varying choices when implementing a VBT. In addition to the
devices shown in Figure 13, functions such as parity and delay lines for control signals could be included. Using
additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and control lines
properly.
The designer may choose to implement an independent clock oscillator at each end of the link and then use a
PLL to synchronize LVDS serdes's parallel I/O to the backplane bus. Resynchronizing FIFOs may also be
required.
Figure 13. Virtual Backplane Transceiver
12
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN65LVDS94DGGRG4 | 功能描述:LVDS 接口集成电路 Serdes Receiver RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
| SN65LVDS95DGG | 功能描述:缓冲器和线路驱动器 Serdes Transmitter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SN65LVDS95DGG | 制造商:Texas Instruments 功能描述:Transceiver IC Transceiver Type:Eia/Tia- |
| SN65LVDS95DGGG4 | 功能描述:LVDS 接口集成电路 Serdes Transmitter RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
| SN65LVDS95DGGR | 功能描述:LVDS 接口集成电路 Serdes Transmitter RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
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