- 您现在的位置：买卖IC网 > PDF目录98091 > SN74ABT16853DLRG4 (TEXAS INSTRUMENTS INC) ABT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56 PDF资料下载
参数资料
| 型号： | SN74ABT16853DLRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 总线收发器 |
| 英文描述： | ABT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封装： | 0.300 INCH, GREEN, PLASTIC, SSOP-56 |
| 文件页数： | 1/11页 |
| 文件大小： | 334K |
| 代理商： | SN74ABT16853DLRG4 |
SN54ABT16853, SN74ABT16853
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
Widebus
Family
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
D Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes
PCB Layout
D High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D Parity-Error Flag With Parity
Generator/Checker
D Latch for Storage of the Parity-Error Flag
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The
’ABT16853
dual
8-bit
to
9-bit
parity
transceivers are designed for communication
between data buses. When data is transmitted
from the A bus to the B bus, a parity bit is
generated. When data is transmitted from the
B bus to the A bus, with its corresponding parity
bit, the open-collector parity-error (ERR) output
indicates whether or not an error in the B data has
occurred. The output-enable (OEA and OEB)
inputs can be used to disable the device so that
the buses are effectively isolated. The ’ABT16853
provide true data at the outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEB
1LE
1ERR
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2ERR
2LE
2OEB
1OEA
1CLR
1PARITY
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2PARITY
2CLR
2OEA
SN54ABT16853 ...WD PACKAGE
SN74ABT16853 . . . DGG OR DL PACKAGE
(TOP VIEW)
Copyright
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC-
ΙΙB and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74ABT18245ADGG | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| SN74ABT18502PMR | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| SN74ABT18502PM | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| SN74ABT18504PMRG4 | ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| SN74ABT18640DGGR | ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74ABT16863 | 制造商:TI 制造商全称:Texas Instruments 功能描述:18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| SN74ABT16863DL | 功能描述:总线收发器 18-Bit Bus Trnscvrs With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| SN74ABT16863DLG4 | 功能描述:总线收发器 18-Bit Bus Trnscvrs With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| SN74ABT16863DLR | 功能描述:总线收发器 18-Bit Bus Trnscvrs With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| SN74ABT16863DLRG4 | 功能描述:总线收发器 18-Bit Bus Trnscvrs With 3-State Outputs RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。