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参数资料
| 型号： | SN74AUP1G17DBVRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 门电路 |
| 英文描述： | AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PDSO5 |
| 封装： | GREEN, PLASTIC, SOT-23, 5 PIN |
| 文件页数： | 12/25页 |
| 文件大小： | 1080K |
| 代理商： | SN74AUP1G17DBVRG4 |
AUP
LVC
AUP
LVC
Static-Power Consumption
(
A)
Dynamic-Power Consumption
(pF)
Single, dual, and triple gates
3.3-V
Logic
3.3-V
Logic
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
0.5
0
0.5
1
1.5
2
2.5
3
3.5
0
5
10
15
20
25
30
35
40
45
Time ns
V
oltage
V
AUP1G08 data at CL = 15 pF
Switching Characteristics
at 25 MHz
Output
Input
SCES579I – JUNE 2004 – REVISED MARCH 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching-noise immunity at the input.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE PART
TOP-SIDE
TA
PACKAGE(2)
NUMBER
MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G17YFPR
_ _ _H7_
0.23-mm Large Bump – YFP (Pb-free)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP1G17YZPR
_ _ _H7_
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY
Reel of 5000
SN74AUP1G17DRYR
H7
uQFN – DSF
Reel of 5000
SN74AUP1G17DSFR
H7
–40°C to 85°C
Reel of 3000
SN74AUP1G17DBVR
SOT (SOT-23) – DBV
H17_
Reel of 250
SN74AUP1G17DBVT
Reel of 3000
SN74AUP1G17DCKR
SOT (SC-70) – DCK
H7_
Reel of 250
SN74AUP1G17DCKT
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G17DRLR
H7_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUT
OUTPUT
A
Y
H
L
2
Copyright 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G17
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PDF描述 |
|---|---|
| SN74AUP1G17MDCKREP | AUP/ULP/V SERIES, 1-INPUT NON-INVERT GATE, PDSO5 |
| SN74AUP1G240DBVT | AUP/ULP/V SERIES, 1-BIT DRIVER, INVERTED OUTPUT, PDSO5 |
| SN74AUP1G240YEPR | AUP/ULP/V SERIES, 1-BIT DRIVER, INVERTED OUTPUT, BGA5 |
| SN74AUP1G32DCKT | AUP/ULP/V SERIES, 2-INPUT OR GATE, PDSO5 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74AUP1G17DBVT | 功能描述:缓冲器和线路驱动器 Lo PWR SNGL Schmitt Trgr Bufr RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SN74AUP1G17DBVTE4 | 功能描述:缓冲器和线路驱动器 Lo PWR SNGL Schmitt Trgr Bufr RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SN74AUP1G17DBVTG4 | 功能描述:缓冲器和线路驱动器 Lo PWR SNGL Schmitt Trgr Bufr RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SN74AUP1G17DCKR | 功能描述:缓冲器和线路驱动器 Lo-Pwr Sgle Schmitt- Trigger Inverter RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
| SN74AUP1G17DCKRE4 | 功能描述:缓冲器和线路驱动器 Lo PWR SNGL Schmitt Trgr Bufr RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
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