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参数资料
| 型号： | SN74AUP3G34YFPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 门电路 |
| 英文描述： | AUP/ULP/V SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PBGA8 |
| 封装： | 0.20 MM, LEAD FREE, WCSP-8 |
| 文件页数： | 1/18页 |
| 文件大小： | 716K |
| 代理商： | SN74AUP3G34YFPR |
DCU PACKAGE
(TOP VIEW)
1
8
2
7
3
6
1A
3Y
2A
GND
4
5
V
CC
1Y
3A
2Y
1
8
2
7
3
6
1A
3Y
2A
GND 4
5
V
CC
1Y
3A
2Y
DQE PACKAGE
(TOP VIEW)
RSE PACKAGE
(TOP VIEW)
1
7
2
6
8
3
5
4
V
CC
1Y
3A
2Y
GND
1A
3Y
2A
1A
3Y
GND
2A
V
CC
1Y
3A
2Y
YFP PACKAGE
(TOP VIEW)
4 5
3 6
2 7
1 8
A1
A2
B1
B2
C1
C2
D1
D2
(A)
Single, dual, and triple gates
Static-Power Consumption
(A)
AUP
AUP
3.3-V
Logic
(A)
0%
20%
40%
60%
80%
100%
Dynamic-Power Consumption
(pF)
AUP
AUP
3.3-V
Logic
(A)
0%
20%
40%
60%
80%
100%
Switching Characteristics
at 25 MHz
(A)
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
30
35
40
45
Time (ns)
V
oltage
(V)
Output
Input
(A) SN74AUP3Gxx data at C = 15 pF.
L
www.ti.com
SCES766B – DECEMBER 2009 – REVISED MARCH 2010
LOW-POWER TRIPLE BUFFER GATE
Check for Samples: SN74AUP3G34
1
FEATURES
Available in the Texas Instruments NanoStar
Optimized for 3.3-V Operation
Package
3.6-V I/O Tolerant to Support Mixed-Mode
Low Static-Power Consumption
Signal Operation
(ICC = 0.9 mA Maximum)
tpd = 4.3 ns Maximum at 3.3 V
Low Dynamic-Power Consumption
Suitable for Point-to-Point Applications
(Cpd = 4.3 pF Typ at 3.3 V)
Latch-Up Performance Exceeds 100 mA Per
Low Input Capacitance (Ci = 1.5 pF Typical)
JESD 78, Class II
Low Noise – Overshoot and Undershoot
ESD Performance Tested Per JESD 22
<10% of VCC
–
2000-V Human-Body Model
Ioff Supports Partial-Power-Down Mode
(A114-B, Class II)
Operation
–
1000-V Charged-Device Model (C101)
Wide Operating VCC Range of 0.8 V to 3.6 V
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Figure 1. AUP – The Lowest-Power Family
Figure 2. Excellent Signal Integrity
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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