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参数资料
| 型号： | SN74AUP3G34YFPR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 门电路 |
| 英文描述： | AUP/ULP/V SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PBGA8 |
| 封装： | 0.20 MM, LEAD FREE, WCSP-8 |
| 文件页数： | 11/18页 |
| 文件大小： | 716K |
| 代理商： | SN74AUP3G34YFPR |
1
7
1A
1Y
3
5
2A
2Y
6
2
3A
3Y
SCES766B – DECEMBER 2009 – REVISED MARCH 2010
www.ti.com
The SN74AUP3G34 performs the Boolean function Y = A in positive logic.
NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE
TOP-SIDE
TA
PACKAGE(2)
PART NUMBER
MARKING(3)
NanoStar – WCSP (DSBGA)
Reel of 3000
SN74AUP3G34YFPR
_ _ H 9 _
0.23-mm Large Bump – YFP (Pb-free)
uQFN – DQE
Reel of 5000
SN74AUP3G34DQER
TZ
–40°C to 85°C
QFN – RSE
Reel of 5000
SN74AUP3G34RSER
TZ
SSOP – DCU
Reel of 3000
SN74AUP3G34DCUR
H34_
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3)
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUT
OUTPUT
A
Y
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
Pin numbers shown are for the DCU and DQE packages.
2
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP3G34
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