参数资料
型号: SN74LV74ANS
厂商: TEXAS INSTRUMENTS INC
元件分类: 锁存器
英文描述: LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封装: PLASTIC, SOP-14
文件页数: 1/8页
文件大小: 150K
代理商: SN74LV74ANS
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381E – AUGUST 1997 – REVISED MAY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Process
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D 2-V to 5.5-V VCC Operation
D Support Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
These dual positive-edge-triggered D-type flip-
flops are designed for 2-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the
setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54LV74A is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74LV74A is characterized for operation from –40
°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
L
H
X
H
L
H
LX
XL
H
L
LX
X
H
HH
L
H
LL
H
L
X
Q0
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
Copyright
2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
SN54LV74A ...J OR W PACKAGE
SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
32 1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
V
2CLR
1Q
GND
NC
SN54LV74A . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
EPIC is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相关PDF资料
PDF描述
SN74LVC00DR LVC/LCX/Z SERIES, QUAD 2-INPUT NAND GATE, PDSO14
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SN74LVC07AQPWRG4Q1 LVC/LCX/Z SERIES, HEX 1-INPUT NON-INVERT GATE, PDSO14
SN74LVC10DB LVC/LCX/Z SERIES, TRIPLE 3-INPUT NAND GATE, PDSO14
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