参数资料
型号: SN74LVTH16652MEAX
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 总线收发器
英文描述: LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
封装: 0.300 INCH, MO-118, SSOP-56
文件页数: 7/9页
文件大小: 87K
代理商: SN74LVTH16652MEAX
7
www.fairchildsemi.com
7
4
L
V
TH16
652
AC Electrical Characteristics
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 10)
Note 10: Capacitance is measured at frequency f
= 1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
TA = 40°C to +85°C
Units
CL = 50 pF, RL = 500
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
150
MHz
tPHL
Propagation Delay
1.3
4.8
1.3
5.4
ns
tPLH
CPAB or CPBA to A or B
1.3
5.1
1.3
5.6
tPHL
Propagation Delay
1.0
4.5
1.0
5.1
ns
tPLH
Data to A or B
1.0
4.4
1.0
4.7
tPHL
Propagation Delay
1.0
4.9
1.0
5.5
ns
tPLH
SBA or SAB to A or B
1.0
4.8
1.0
5.4
tPZL
Output Enable Time
1.0
4.9
1.0
5.8
ns
tPZH
OE to A
1.04.8
1.05.8
tPLZ
Output Disable Time
1.6
5.6
1.6
6.1
ns
tPHZ
OE to A
2.05.4
2.06.1
tPZL
Output Enable Time
1.3
5.0
1.3
5.4
ns
tPZH
OE to B
1.3
4.8
1.3
5.4
tPLZ
Output Disable Time
1.3
5.5
1.3
6.2
ns
tPHZ
OE to B
1.3
5.6
1.3
6.3
tS
Setup Time
A or B before CPAB or CPBA, Data HIGH
1.2
1.5
ns
A or B before CPAB or CPBA, Data LOW
2.0
2.8
tH
Hold Time
A or B before CPAB or CPBA, Data HIGH
0.5
0.0
ns
A or B before CPAB or CPBA, Data LOW
0.5
tW
Pulse Width
CPAB or CPBA HIGH or LOW
3.3
ns
tOSHL
Output to Output Skew (Note 9)
1.0
ns
tOSLH
1.0
Symbol
Parameter
Conditions
Typical
Units
CIN
Input Capacitance
VCC = Open, VI = 0V or VCC
4pF
CI/O
Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
8pF
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