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| 型号： | SN74V273-15GGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器 |
| 文件页数： | 11/52页 |
| 文件大小： | 762K |
| 代理商： | SN74V273-15GGM |
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SN74V263, SN74V273, SN74V283, SN74V293
8192
×
18, 16384
×
18, 32768
×
18, 65536
×
18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D
–
JUNE 2001
–
REVISED FEBRUARY 2003
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
read enable (REN)
When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK
cycle, if the device is not empty.
When REN is high, the output register holds the previous data and no new data is loaded into the output register.
The data outputs Q0
–
Qn maintain the previous data value.
In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn on the third
valid low-to-high transition of RCLK + t
sk
after the first write. REN does not need to be asserted low. To access
all other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has
been read from the FIFO, OR goes high with a true read (RCLK with REN = low), inhibiting further read
operations. REN is ignored when the FIFO is empty.
In the standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be
requested using REN. When the last word has been read from the FIFO, EF goes low, inhibiting further read
operations. REN is ignored when the FIFO is empty. Once a write is performed, EF goes high, allowing a read
to occur. The EF flag is updated by two RCLK cycles + t
sk
after the valid WCLK cycle.
serial enable (SEN)
The SEN input is an enable used only for serial programming of the offset registers. The serial programming
method must be selected during master reset. SEN always is used with LD. When these lines are both low, data
at the SI input can be loaded into the program register, with one bit for each low-to-high transition of WCLK.
When SEN is high, the programmable registers retain the previous settings and no offsets are loaded. SEN
functions the same way in FWFT and standard modes.
output enable (OE)
When OE is asserted (low), the parallel output buffers receive data from the output register. When OE is high,
the output data bus (Qn) goes into the high-impedance state.
load (LD)
LD is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1,
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After master reset, LD enables write
operations to and read operations from the offset registers. Only the offset loading method currently selected
can be used to write to the registers. Offset registers can be read only in parallel.
After master reset, LD is used to activate the programming process of the flag offset values PAE and PAF. Pulling
LD low begins a serial loading, or a parallel load, or a read of these offset values.
input width (IW)/output width (OW) bus matching
IW and OW define the input and output bus widths. During master reset, the state of these pins is used to
configure the device bus sizes (see Table 1 for control settings). All flags operate based on the word/byte size
boundary, as defined by the selection of the widest input or output bus width.
big endian/little endian (BE)
During master reset, a low on BE selects big-endian operation. A high on BE during master reset selects
little-endian format. This function is useful when data is written into the FIFO in word format (
×
18) and read out
of the FIFO in word format (
×
18) or byte format (
×
9). If big-endian mode is selected, the MSB of the word written
into the FIFO is read out of the FIFO first, followed by the LSB. If little-endian format is selected, the LSB of the
word written into the FIFO is read out first, followed by the MSB. The desired mode is configured during master
reset by the state of the BE.
See Figure 4 for the byte arrangement.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V273-6GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V273-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V283-10GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V283-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V283-6GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V273-15PZA | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-6GGM | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-6PZA | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-7GGM | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V273-7PZA | 功能描述:先进先出 16384 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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