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| 型号： | SN74V283-15GGM |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 8192】18，16384】18，32768】18，65536】18的3.3V的CMOS先入先出存储器 |
| 文件页数： | 13/52页 |
| 文件大小： | 762K |
| 代理商： | SN74V283-15GGM |
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SN74V263, SN74V273, SN74V283, SN74V293
8192
×
18, 16384
×
18, 32768
×
18, 65536
×
18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D
–
JUNE 2001
–
REVISED FEBRUARY 2003
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
empty flag/output ready (EF/OR)
EF/OR is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time that
the first word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high
transition that shifts the last word from the FIFO memory to the outputs. OR goes high only with a true read
(RCLK with REN = low). The previous data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes low again.
See Figure 10 for timing information.
In the standard mode, the EF function is selected. When the FIFO is empty, EF goes low, inhibiting further read
operations. When EF is high, the FIFO is not empty.
See Figure 8 for timing information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In FWFT mode, OR is a triple register-buffered output. In standard mode, EF is a double register-buffered
output.
programmable almost-full flag (PAF)
PAF goes low when the FIFO reaches the almost-full condition. In FWFT mode, if
×
18 input or
×
18 output bus
width is selected, PAF goes low after (8193
–
m) writes for the SN74V263, (16385
–
m) writes for the SN74V273,
(32769
–
m) writes for the SN74V283, and (65537
–
m) writes for the SN74V293. If both
×
9 input and
×
9 output
bus widths are selected, PAF goes low after (16385
–
m) writes for the SN74V263, (32769
–
m) writes for the
SN74V273, (65537
–
m) writes for the SN74V283, and (131073
–
m) writes for the SN74V293. The offset m
is the full offset value. The default setting for this value is shown in Table 2.
In standard mode, if no reads are performed after MRS, PAF goes low after (D
–
m) words are written to the
FIFO. If
×
18 input or
×
18 output bus width is selected, (D
–
m) = (8192
–
m) writes for the SN74V263, (16384
–
m)
writes for the SN74V273, (32768
–
m) writes for the SN74V283, and (65536
–
m) writes for the SN74V293. If
both
×
9 input and
×
9 output bus widths are selected, (D
–
m) = (16384
–
m) writes for the SN74V263,
(32768
–
m) writes for the SN74V273, (65536
–
m) writes for the SN74V283, and (131072
–
m) writes for the
SN74V293. The offset m is the full offset value. The default setting for this value is shown in Table 2.
See Figure 18 for timing information.
If asynchronous PAF configuration is selected, the PAF is asserted low on the low-to-high transition of WCLK.
PAF is reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected, the PAF
is updated on the rising edge of WCLK (see Figure 20).
programmable almost-empty flag (PAE)
PAE goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there
are n + 1 words, or fewer, in the FIFO. The default setting for this value is shown in Table 2.
In standard mode, PAE goes low when there are n words, or fewer, in the FIFO. The offset n is the empty offset
value. The default setting for this value is shown in Table 2.
See Figure 19 for timing information.
If asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of the read clock
(RCLK). PAE is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE
configuration is selected, PAE is updated on the rising edge of RCLK.
See Figure 21 for timing information.
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V283-6GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V283-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V293-10GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V293-15GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V293-7GGM | 8192 】 18, 16384 】 18, 32768 】 18, 65536 】 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V283-15PZA | 功能描述:先进先出 32768 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V283-15PZAG4 | 制造商:Texas Instruments 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 32KX18/64KX9 80LQFP - Rail/Tube |
| SN74V283-6GGM | 功能描述:先进先出 32768 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V283-6PZA | 功能描述:先进先出 32768 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V283-7GGM | 功能描述:先进先出 32768 x 18 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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