参数资料
型号: SP3203EEY
元件分类: RS-232
英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述: 5V的高速RS - 232收发器与0.1uF电容
文件页数: 8/16页
文件大小: 509K
代理商: SP3203EEY
Rev.
2/7
/01
SP3203E
8
Copyright 2001 Sipex Corporation
DESCRIPTION
The SP3203E is a 3-driver/2-receiver device that
can be operated as a full duplex, RS-232 serial
transceiver with the 3rd driver acting as a control
line allowing a Ring Indicator (RI) signal to alert
the UART on the PC.
This
transceiver meet the EIA/TIA-232 and ITU-
T V.28/V.24 communication protocols and can
be implemented in battery-powered, portable, or
hand-held applications such as notebook or
palmtop computers, PDA's and cell phones. The
SP3203E devices feature Sipex's proprietary and
patented (U.S.
#
5,306,954) on-board charge pump
circuitry that generates
±
5.5V RS-232 voltage
levels from a single +3.0V to +5.5V power
supply. The SP3203E devices can operate at a
minimum data range of 250kbps, driving a single
driver. The SP3203E is a 3-driver/2-receiver
device.
THEORY OF OPERATION
The SP3203E contains four basic circuit blocks:
1. drivers, 2. receivers, 3. a Sipex proprietary
charge pump and 4. V
L
circuitry.
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative to
the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to
ground without degradation in reliability. These
drivers comply with the EIA-TIA-232F and all
previous RS-232 versions. The driver output
stages are turned off (High Impedance) when
the device is in shutdown mode.
The drivers typically can operate at a data rate
of 250Kbps. The drivers can guarantee a data
rate of 120Kbps fully loaded with 3K
in
parallel with 1000pF, ensuring compatibility
with PC-to-PC communication software.
The slew rate of the driver output is internally
limited to a maximum of 30V/
μ
s in order to
meet the EIA standards (EIA RS-232D 2.1.7,
Paragraph 5). The transition of the loaded
output from HIGH to LOW also meets the
monotonicity requirements of the standard.
The SP3203E driver can maintain high data
rates up to 250Kbps with a single driver loaded.
Figure 9
shows a loopback test circuit used to
test the RS-232 Drivers. Figure 10
shows the
test results of the loopback circuit with all three
drivers active at 120Kbps with typical RS-232
loads in parallel with 1000pF capacitors. Figure
11
shows the test results where one driver was
active at 250Kbps and all three drivers loaded
with an RS-232 receiver in parallel with a 1000pF
capacitor. The transmitter inputs do not have
pull-up resistors. Connect unused inputs to
ground or V
L
Receivers
The receivers convert
±
5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels.
Receivers are disabled when in shutdown. The
truth table logic of the
SP3203E driver and
receiver outputs can be found in Table 1.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 500mV. This
ensures that the receiver is immune to noisy
transmission lines. Should an input be left un-
connected, an internal 5K
pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. #5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
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