参数资料
型号: SP6132HEU-L
厂商: Exar Corporation
文件页数: 4/14页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 10-MSOP
标准包装: 50
PWM 型: 电压模式
输出数: 1
频率 - 最大: 360kHz
占空比: 100%
电源电压: 4.5 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 管件
FUNCTIONAL DIAGRAM
5 COMP
100% Protection Logic
PULSES CLR
FAULT
VCC
PWM LOOP
COUNT 20
CLOCK
CLK
10 BST
VFB
VCC
VFBINT
VCC
Gm ERROR AMPLIFIER
Gm
VPOS
FAULT
FAULT
RESET
DOMINANT
R
QPWM
Q
S
SYNCHRONOUS
DRIVER
9 GH
8 SWN
2 GL
10 μ A
SS 7
SOFTSTART INPUT
POS REF
300 kHZ
FAULT
RAMP = 1.1V
0.4 V
CLK
CLOCK PULSE GENERATOR
SS
GL HOLD OFF
V CC 1
REFERENCE
CORE
0.8V
REF OK
1.7 V
1.7 V
ASYNC. STARTUP
3 GND
COMPARATOR
145 ?C ON
135 ?C OFF
THERMAL
SHUTDOWN
SET
DOMINANT
S
VPOS
0.25 V
+-
SHORT CIRCUIT
DETECTION
+
Q
HICCUP FAULT
REF OK
FAULT
VFBINT
-
R
VCC
+
4.25 V ON
4.05 V OFF -
VCC UVLO
POWER FAULT
+
CLK
6
2.50 VON
2.20 V OFF
-
VIN UVLO
COUNTER
200ms Delay
UVIN
CLR
REF OK
THERMAL AND SHORT CIRCUIT PROTECTION
UVLO COMPARATORS
THEORY OF OPERATION
General Overview
The SP6132H is a fixed frequency, voltage
mode, synchronous PWM controller optimized
for high efficiency. The part has been designed
to be especially attractive for split plane applica-
tions which utilize 5V to power the controller
and 3V to 12V for step down conversion.
The heart of the SP6132H is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. A precision 0.8V reference present on
the positive terminal of the error amplifier per-
mits the programming of the output voltage
down to 0.8V via the V FB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp and PWM
control logic are governed by the internal oscil-
lator that accurately sets the PWM frequency to
300kHz.
The SP6132H contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during start up to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The SP6132H also contains a number of valu-
able protection features. A programmable input
(V IN ) UVLO allows a user to set the exact value
at which the conversion voltage is at a safe point
to begin down conversion, and an internal V CC
UVLO ensures that the controller itself has
enough voltage to properly operate. Other pro-
Date:2/14/06
SP6132H High Voltage, Synchronous PWM Controller
4
? Copyright 2006 Sipex Corporation
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