参数资料
型号: SP7653ER-L/TR
厂商: Exar Corporation
文件页数: 9/15页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 3A 26DFN
标准包装: 3,000
系列: Power Blox™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 19 V
输入电压: 2.5 V ~ 20 V
PWM 型: 电压模式
频率 - 开关: 1.3MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 26-VFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 26-DFN(7x4)
APPLICATIONS INFORMATION
The capacitor type suitable for the output capac-
itors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitors are used. Tantalum capacitors are known
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“live” to low impedance power sources. Although
tantalum capacitors have been successfully em-
The first step of compensation design is to pick
the loop crossover frequency. High crossover
frequency is desirable for fast transient response,
but often jeopardizes the power supply stability.
Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching
frequency or 60kHz. The ESR zero is contrib-
uted by the ESR associated with the output
capacitors and can be determined by:
ployed at the input, it is generally not recom-
mended.
? Z(ESR) =
1
2 C OUT R ESR
? P(LC) =
LoopCompensationDesign
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the desired frequency cut-off (FCO), the
gain of the error amplifier must compensate for
the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation
is to manipulate loop frequency response such
that its crossover gain at 0db, results in a slope
of -20db/dec.
The next step is to calculate the complex conju-
gate poles contributed by the LC output filter,
1
2 L C OUT
When the output capacitors are Ceramic, the
SP7653 Evaluation Board requires a Type III
compensation circuit to give a phase boost of
180 ° in order to counteract the effects of an
underdamped resonance of the output filter at
the double pole frequency.
Type III Voltage Loop
Compensation
G AMP (s) Gain Block
PWM Stage
G PWM Gain
Block
Output Stage
G OUT (s) Gain
Block
V REF
(Volts)
+
_
(SRz2Cz2+1)(SR1Cz3+1)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
V IN
V RAMP_PP
(SR ESR C OUT + 1)
[S^2LC OUT +S(R ESR +R DC ) C OUT +1]
V OUT
(Volts)
Notes: R ESR = Output Capacitor Equivalent Series Resistance.
R DC = Output Inductor DC Resistance.
V RAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R ESR & R DC
Voltage Feedback
G FBK Gain Block
V FBK
(Volts)
R 2
(R 1 + R 2 )
or
V REF
V OUT
SP7653 Voltage Mode Control Loop with Loop Dynamic
Definitions:
R ESR = Output Capacitor Equivalent Series Resistance
R DC = Output Inductor DC Resistance
R RAMP_PP = SP7653 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
C Z 2 >> Cp1 and R1 >> Rz3
Output Load Resistance >> R ESR and R DC
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
2/17/06
Date:   /20/06
SP7653 Wide Input Voltage Range,  .3MHz, Buck Regulator
9  
? Copyright 2006 Sipex Corporation
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