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参数资料
| 型号： | SPAK5307FT90B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 90 MHz, RISC PROCESSOR, PQFP208 |
| 封装： | 28 X 28 MM, PLASTIC, QFP-208 |
| 文件页数： | 4/30页 |
| 文件大小： | 117K |
| 代理商： | SPAK5307FT90B |
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12
MCF5307 Product Brief
MOTOROLA
Programming Model, Instruction Set, and Addressing Mode
Overview
The ColdFire programming model is separated into two privilege modes:
supervisor and user. The S-bit in the status register (SR) indicates the current
privilege mode. The processor identies a logical address by accessing either
the supervisor or user address space, which differentiates between supervisor
and user modes.
Supervisor Mode
Supervisor mode protects system resources from uncontrolled access by
users. In supervisor mode, you can access all registers and execute all
ColdFire instructions. Operating system functions (including I/O control) are
performed while in supervisor mode. During exception processing, the
processor enters supervisor mode regardless of the operating mode at the time
of the exception.
Typically, system programmers use the supervisor programming model to
implement operating system functions and provide I/O control. The
supervisor programming model provides access to the same registers as the
user model, plus seven additional registers. These added resources include the
upper byte of the Status Register (SR), the Vector Base Register (VBR), plus
ve registers dening the conguration and attributes of the address space
connected to the MCF5307.
User Mode
While in user mode, access to only a subset of the supervisor registers is
allowed, and execution of privileged instructions is not permitted. Typically,
most application processing occurs while in user mode. Entry into user mode
is usually accomplished by executing a “return from exception” (RTE) or
MOVE, SR instruction.
User Programming
Model
The registers depicted in the programming model (see Figure 2) provide high-
speed storage for data and addresses for the ColdFire processor core. The user
programming model consists of sixteen general-purpose 32-bit registers {D0-
D7, A0-A7} plus two additional registers: the program counter (PC) and the
condition code register (CCR).
The program counter is a 32-bit register containing the address of the
instruction currently being executed by the MCF5307 processor. The 8-bit
CCR contains indicator ags that reect the result of a previous operation and
are used for conditional instruction execution.
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