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参数资料
| 型号： | SPAK5307FT90B |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 90 MHz, RISC PROCESSOR, PQFP208 |
| 封装： | 28 X 28 MM, PLASTIC, QFP-208 |
| 文件页数： | 5/30页 |
| 文件大小： | 117K |
| 代理商： | SPAK5307FT90B |
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MOTOROLA
MCF5307 Product Brief
13
Programming Model, Instruction Set, and Addressing Mode,
Continued
Status Register (SR)
The upper byte of the Status Register provides interrupt information in
addition to a variety of mode indicators signaling the operating state of the
ColdFire processor.
Vector Base Register
(VBR)
The VBR denes the upper 12 bits of the base address of the exception vector
table used during exception processing. The low-order 20 bits are forced to
zero, placing the vector table on a 0-modulo-1Mbyte address boundaries,
which is set by the upper 12 bits of the address.
Cache Control
Register (CCR)
The Cache Control Register (CACR) denes the conguration of the unied
cache and provides a set of default address attributes.
Access Control
Registers (ACRs)
There are two Access Control Registers (ACR0, ACR1), which each dene a
set of address attributes for a specic memory space. For example, a memory
space can be dened as copyback, writethrough, or noncacheable using the
ACR registers.
RAM Base Address
Register (RAMBAR)
The RAM Base Address Register (RAMBAR) provides the logical base
address for the processor's 4 Kbyte SRAM module as well as denition of
those access types that are allowed to access that SRAM.
Module Base Address
Register (MBAR)
The Module Base Address Register (MBAR) denes the logical base address
for the memory-mapped space containing the control registers for the on-chip
peripherals.
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