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Register Descriptions (ESSI0_BASE = $1FFE20, ESSI1_BASE = $1FFE00)
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
12-31
Preliminary
12
Note:
All flags in the status portion of the SSR are updated after the first bit of the
next ESSI word has completed transmission or reception. The ROE and TUE
status bits are cleared by reading the SSR followed by a read/write to either the
SRX or STX0-2 register, respectively.
Note:
The RLS and TLS status bits are cleared by reading the SSR, then writing a 1 to
the appropriate bit of the SSR.
12.7.7.1 Input Flag 1 (IF1)—Bit 15
The IF1 bit is enabled only when SC1 is configured as an input flag and the Synchronous
mode is selected. For example, when the SYN bit is set and the TE2 and SCD1 bits are
The ESSI latches any data present on the SC1 signal during reception of the first received
bit after the frame sync is detected. The IF1 bit is updated with this data when the data in
the receive shift register is transferred into the receive data register
If it is not enabled, the IF1 bit is cleared.
12.7.7.2 Input Flag 0 (IF0)—Bit 14
The IF0 bit is enabled only when SC0 is configured as an input flag and the Synchronous
mode is selected; that is, when the SYN bit is set and the TE1 and SCD0 bits are cleared.
The ESSI latches any data present on the SC0 signal during reception of the first received
bit after the frame sync is detected. The IF0 bit is updated with this data when the data in
the Receive Shift Register is transferred into the Receive Data Register. If it is not
enabled, the IF0 bit is cleared.
12.7.7.3 Reserved—Bit 13
This bit is reserved or not implemented. It cannot be read or modified by writing.
12.7.7.4 Transmit FIFO Full (TFF)—Bit 12
This status bit allows the user to monitor when the Transmit FIFO is full. The state of this
bit reflects the status of the transmitter(s) selected by the TXSF0-2 control bits.
0 = Transmit FIFO can accept more data
1 = Transmit FIFO is full