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16-12
DSP56853/854/855/857/858 User’s Manual
MOTOROLA
Preliminary
DSP Side Registers
16
16.8.1.8 Host Transmit Interrupt Enable (HTIE)—Bit 1
The Host Transmit Interrupt Enable (HTIE) bit is used to enable a DSP core interrupt
when the Host Transmit Data Empty (HTDE) status bit in the HSR is set. When the HTIE
bit is cleared, HTDE interrupts are disabled. When the HTIE bit is set, a Host Transmit
Data Interrupt request occurs when the HTDE bit is set. The HTIE bit is cleared on
hardware reset.
16.8.1.9 Host Receive Interrupt Enable (HRIE)—Bit 0
The Host Receive Interrupt Enable (HRIE) bit is used to enable a DSP core interrupt when
the Host Receive Data Full (HRDF) status bit in the Host Status Register (HSR) is set.
When the HRIE bit is cleared, HRDF interrupts are disabled. When the HRIE bit is set, a
Host Receive Data Interrupt request occurs if the HRDF bit is also set. The HRIE bit is
cleared on hardware reset.
16.8.2 HI8 Status Register (HSR)
The HI8 Status Register (HSR) is a 16-bit read-only status register used by the DSP to
read the status and flags of the HI8 interface. It cannot be directly accessed by the Host
Processor. Reserved bits are read as 0s. The value of the HSR after reset is $0002. All bits
are cleared, except for the Host Transmit Data Empty (HTDE) bit. It is set. The HSR bits
are described in the following paragraphs.
Figure 16-4. Host Status Register (HSR)
16.8.2.1 Reserved—Bits 15-6
These bits are reserved or not implemented. They are read as, and written with 0s.
16.8.2.2 Host DMA Status (HDMA)—Bit 5
The Host DMA Status (HDMA) bit indicates the Host Processor has enabled the Host
DMA mode of the HI8 by setting HM1 or HM0 to 1. When the HDMA status bit is set at
0, it indicates the Host DMA mode is disabled by the Host mode bits HM0 and HM1, both
having been cleared, in the Interface Control Register ICR and no Host DMA operations
are pending. When the HDMA status bit is set, the Host DMA mode is enabled by the
$1FFFD8 + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
HDMA
HFI
HF0
HCP
HTDE HRDF
Write
0
RESET
00
0
00
0
000
000010