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| 型号： | SPAKDSP321VL240 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 2/84页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 240MHZ 196-MAPBGA |
| 标准包装： | 2 |
| 系列： | DSP56K/Symphony |
| 类型： | 定点 |
| 接口： | 主机接口，SSI，SCI |
| 时钟速率： | 240MHz |
| 非易失内存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.60V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LBGA |
| 供应商设备封装： | 196-MAPBGA（15x15） |
| 包装： | 托盘 |
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DSP56321 Technical Data, Rev. 11
1-4
Freescale Semiconductor
Signals/Connections
1.4 External Memory Expansion Port (Port A)
Note:
When the DSP56321 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals: A[0–17], D[0–23], AA[0–3], RD, WR, BB.
1.4.1
External Address Bus
1.4.2
External Data Bus
1.4.3
External Bus Control
Table 1-5.
External Address Bus Signals
Signal Name
Type
State During
Reset, Stop,
or Wait
Signal Description
A[0–17]
Output
Tri-stated
Address Bus—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
Table 1-6.
External Data Bus Signals
Signal Name
Type
State During
Reset
State During
Stop or Wait
Signal Description
D[0–23]
Input/ Output
Ignored Input
Last state:
Input: Ignored
Output:
Last value
Data Bus—When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data
memory accesses. Otherwise, D[0–23] drivers are tri-
stated. If the last state is output, these lines have weak
keepers to maintain the last output state if all drivers are tri-
stated.
Table 1-7.
External Bus Control Signals
Signal Name
Type
State During
Reset, Stop, or
Wait
Signal Description
AA[0–3]
Output
Tri-stated
Address Attribute—When defined as AA, these signals can be used as chip
selects or additional address lines. The default use defines a priority scheme
under which only one AA signal can be asserted at a time. Setting the AA priority
disable (APD) bit (Bit 14) of the Operating Mode Register, the priority
mechanism is disabled and the lines can be used together as four external lines
that can be decoded externally into 16 chip select signals.
RD
Output
Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low output that
is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is
tri-stated.
WR
Output
Tri-stated
Write Enable—When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D[0–23]). Otherwise,
the signals are tri-stated.
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