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| 型号： | SPAKDSP321VL240 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/84页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 240MHZ 196-MAPBGA |
| 标准包装： | 2 |
| 系列： | DSP56K/Symphony |
| 类型： | 定点 |
| 接口： | 主机接口，SSI，SCI |
| 时钟速率： | 240MHz |
| 非易失内存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.60V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LBGA |
| 供应商设备封装： | 196-MAPBGA（15x15） |
| 包装： | 托盘 |
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External Memory Expansion Port (Port A)
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
1-5
TA
Input
Ignored Input
Transfer Acknowledge—If the DSP56321 is the bus master and there is no
external bus activity, or the DSP56321 is not the bus master, the TA input is
ignored. The TA input is a data transfer acknowledge (DTACK) function that can
extend an external bus cycle indefinitely. Any number of wait states (1,
2. . .infinity) can be added to the wait states inserted by the bus control register
(BCR) by keeping TA deasserted. In typical operation, TA is deasserted at the
start of a bus cycle, is asserted to enable completion of the bus cycle, and is
deasserted before the next bus cycle. The current bus cycle completes one
clock period after TA is asserted synchronous to CLKOUT. The number of wait
states is determined by the TA input or by the BCR, whichever is longer. The
BCR can be used to set the minimum number of wait states in external bus
cycles.
To use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion;
otherwise, improper operation may result.
BR
Output
Reset: Output
(deasserted)
State during
Stop/Wait
depends on BRH
bit setting:
BRH = 0: Output
(deasserted)
BRH = 1:
Maintains last
state (that is, if
asserted, remains
asserted)
Bus Request—Asserted when the DSP requests bus mastership. BR is
deasserted when the DSP no longer needs the bus. BR may be asserted or
deasserted independently of whether the DSP56321 is a bus master or a bus
slave. Bus “parking” allows BR to be deasserted even though the DSP56321 is
the bus master. (See the description of bus “parking” in the BB signal
description.) The bus request hold (BRH) bit in the BCR allows BR to be
asserted under software control even though the DSP does not need the bus.
BR is typically sent to an external bus arbitrator that controls the priority,
parking, and tenure of each master on the same external bus. BR is affected
only by DSP requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the bus slave
state.
BG
Input
Ignored Input
Bus Grant—Asserted by an external bus arbitration circuit when the DSP56321
becomes the next bus master. When BG is asserted, the DSP56321 must wait
until BB is deasserted before taking bus mastership. When BG is deasserted,
bus mastership is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one external bus
cycle for execution.
To ensure proper operation, the user must set the asynchronous bus arbitration
enable (ABE) bit (Bit 13) in the Operating Mode Register. When this bit is set,
BG and BB are synchronized internally. This adds a required delay between the
deassertion of an initial BG input and the assertion of a subsequent BG input.
BB
Input/ Output
Ignored Input
Bus Busy—Indicates that the bus is active. Only after BB is deasserted can the
pending bus master become the bus master (and then assert the signal again).
The bus master may keep BB asserted after ceasing bus activity regardless of
whether BR is asserted or deasserted. Called “bus parking,” this allows the
current bus master to reuse the bus without rearbitration until another device
requires the bus. BB is deasserted by an “active pull-up” method (that is, BB is
driven high and then released and held high by an external pull-up resistor).
Notes:
1.
See BG for additional information.
2.
BB requires an external pull-up resistor.
Table 1-7.
External Bus Control Signals (Continued)
Signal Name
Type
State During
Reset, Stop, or
Wait
Signal Description
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