参数资料
型号: SPC5566MVR144
厂商: Freescale Semiconductor
文件页数: 32/54页
文件大小: 0K
描述: MCU 3MB FLASH 144MHZ 416-PBGA
标准包装: 200
系列: MPC55xx Qorivva
核心处理器: e200z6
芯体尺寸: 32-位
速度: 144MHz
连通性: CAN,EBI/EMI,以太网,SCI,SPI
外围设备: DMA,POR,PWM,WDT
输入/输出数: 256
程序存储器容量: 3MB(3M x 8)
程序存储器类型: 闪存
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.35 V ~ 1.65 V
数据转换器: A/D 40x12b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 416-BBGA
包装: 托盘
MPC5510 Microcontroller Family Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
38
2.13.3
JTAG (IEEE 1149.1) Interface
Figure 8. JTAG Test Clock Input Timing
Table 21. JTAG Interface Timing1
1 These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0V to 5.5V, T
A = TL to TH, and CL
= 30pF with SRC = 0b11.
Num
Characteristic
Symbol
Min
Max
Unit
1TCK Cycle Time
tJCYC
100
ns
2
TCK Clock Pulse Width (Measured at VDDE/2)
tJDC
40
60
ns
3
TCK Rise and Fall Times (40% – 70%)
tTCKRISE
—3
ns
4
TMS, TDI Data Setup Time
tTMSS, tTDIS
5—
ns
5
TMS, TDI Data Hold Time
tTMSH, tTDIH
25
ns
6
TCK Low to TDO Data Valid
tTDOV
—20
ns
7
TCK Low to TDO Data Invalid
tTDOI
0—
ns
8
TCK Low to TDO High Impedance
tTDOHZ
—20
ns
9
JCOMP Assertion Time
tJCMPPW
100
ns
10
JCOMP Setup Time to TCK Low
tJCMPS
40
ns
11
TCK Falling Edge to Output Valid
tBSDV
—50
ns
12
TCK Falling Edge to Output Valid out of High Impedance
tBSDVZ
—50
ns
13
TCK Falling Edge to Output High Impedance
tBSDHZ
—50
ns
14
Boundary Scan Input Valid to TCK Rising Edge
tBSDST
50
ns
15
TCK Rising Edge to Boundary Scan Input Invalid
tBSDHT
50
ns
TCK
1
2
3
2
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