参数资料
型号: SPC560B50L3C5E0R
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-100
文件页数: 60/74页
文件大小: 971K
代理商: SPC560B50L3C5E0R
Electrical characteristics
SPC560Bx, SPC560Cx
Doc ID 14619 Rev 4
tADC_C CC P Conversion time
(6)
fADC = 32 MHz,
ADC_conf_comp = 2
0.625
s
CS
CC D
ADC input sampling
capacitance
——
3
pF
CP1
CC D
ADC input pin
capacitance 1
——
3
pF
CP2
CC D
ADC input pin
capacitance 2
——
1
pF
CP3
CC D
ADC input pin
capacitance 3
——
1
pF
RSW1
CC D
Internal resistance of
analog source
——
3
k
Ω
RSW2
CC D
Internal resistance of
analog source
2
k
Ω
RAD
CC D
Internal resistance of
analog source
——
0.1
k
Ω
IINJ
SR — Input current Injection
Current
injection on
one ADC
input, different
from the
converted one
VDD = 3.3 V ± 10%
5—
5
mA
VDD = 5.0 V ± 10%
5
5
| INL |
CC T
Absolute value for
integral non-linearity
No overload
0.5
1.5
LSB
| DNL | CC T
Absolute differential
non-linearity
No overload
0.5
1.0
LSB
| OFS | CC T Absolute offset error
0.5
LSB
| GNE | CC T Absolute gain error
——
0.6
LSB
1.
VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2.
Analog and digital VSS must be common (to be tied together externally).
3.
VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion
will be clamped respectively to 0x000 or 0x3FF.
4.
Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal
divider by 2.
5.
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the
sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tADC_S depend on programming.
6.
This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to
load the result’s register with the conversion result.
Table 44.
ADC conversion characteristics (continued)
Symbol
C
Parameter
Conditions(1)
Value
Unit
Min
Typ
Max
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SPC560B50L3C5E0Y 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP100
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