参数资料
型号: SPC560B50L5C5E0Y
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-144
文件页数: 11/74页
文件大小: 971K
代理商: SPC560B50L5C5E0Y
Electrical characteristics
SPC560Bx, SPC560Cx
Doc ID 14619 Rev 4
Note:
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
Table 9.
Recommended operating conditions (5.0 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
0
V
VDD
(1)
SR
Voltage on VDD_HV pins with respect to
ground (VSS)
—4.5
5.5
V
Voltage drop(2)
3.0
5.5
VSS_LV
(3)
SR
Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_BV
(4)
SR
Voltage on VDD_BV pin (regulator supply)
with respect to ground (VSS)
—4.5
5.5
V
Voltage drop(2)
3.0
5.5
Relative to VDD
VDD0.1 VDD+0.1
VSS_ADC
SR
Voltage on VSS_HV_ADC (ADC
reference) pin with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_ADC
(5)
SR
Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—4.5
5.5
V
Voltage drop(2)
3.0
5.5
Relative to VDD
VDD0.1 VDD+0.1
VIN
SR
Voltage on any GPIO pin with respect to
ground (VSS)
—VSS0.1
V
Relative to VDD
—VDD+0.1
IINJPAD
SR
Injected input current on any pin during
overload condition
55
mA
IINJSUM
SR
Absolute sum of all injected input currents
during overload condition
50
TVDD
SR VDD slope to ensure correct power up
(6)
0.25
V/s
—3
V/s
TA C-Grade Part SR Ambient temperature under bias
fCPU < 64 MHz
40
85
°C
TJ C-Grade Part SR Junction temperature under bias
40
110
TA V-Grade Part
SR Ambient temperature under bias
fCPU < 64 MHz
40
105
TJ V-Grade Part
SR Junction temperature under bias
40
130
TA M-Grade Part SR Ambient temperature under bias
fCPU < 60 MHz
40
125
TJ M-Grade Part SR Junction temperature under bias
40
150
1.
100 nF capacitance needs to be provided between each VDD/VSS pair.
2.
Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.6 V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits.
3.
330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4.
470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5.
100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6.
Guaranteed by device validation
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