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参数资料
| 型号： | SPL505YC256BTT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 21/27页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK505 BEARLAKE 56TSSOP |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，PCI Express（PCIe） |
| 输入： | 晶体 |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:22 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 400MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
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SPL505YC25
......................Document #: 001-03543 Rev *E Page 3 of 27
30
SRC5/CPU_STOP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs/100 MHz Differential serial
reference clocks.
31
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
32
SRC6#
O, DIF 100 MHz Differential serial reference clocks.
33
SRC6
O, DIF 100 MHz Differential serial reference clocks.
34
VSS_SRC
GND
Ground for outputs.
35
SRC7#/OE#_6
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#6 Input controlling
SRC6. Default SRC7.
36
SRC7/OE#_8
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8. Default SRC7.
37
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
38
SRC8#/CPUT2_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
39
SRC8/CPUC2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
40
IO_VOUT
O
Integrated Linear Regulator Control.
41
VDD_CPU_IO
PWR
0.7V Power supply for CPU outputs.
42
CPU1#
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode
depending on the configuration set in Byte 11 Bit3:2.
43
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode
depending on the configuration set in Byte 11 Bit3:2.
44
VSS_CPU
GND
Ground for outputs.
45
CPU0#
O, DIF Differential CPU clock outputs.
46
CPU0
O, DIF Differential CPU clock outputs.
47
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
48
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
49
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
50
VSS_REF
GND
Ground for outputs.
51
XOUT
O, SE 14.318 MHz Crystal output.
52
XIN
I
14.318 MHz Crystal input.
53
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
54
REF0/FSC/TEST_SEL
I/O
3.3V tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C speci-
fications.
55
SMB_DATA
I/O
SMBus compatible SDATA.
56
SMB_CLK
I
SMBus compatible SCLOCK.
Pin Definitions (continued)
Pin No.
Name
Type
Description
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