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参数资料
| 型号： | SPL61A |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 80KB LCD Controller/Driver |
| 中文描述： | 80kb左右LCD控制器/驱动器 |
| 文件页数： | 5/15页 |
| 文件大小： | 737K |
| 代理商： | SPL61A |
SPL61A
5. FUNCTIONAL DESCRIPTIONS
5.1. ROM Area
SPL61A is a large ROM based micro-controller with 640 dots LCD
driver. The large ROM can be defined as program ROM, LCD
fonts and audio data continuously without any limitation. To
access the ROM area, users should first program the BANK
SELECT Register ($07) and then access the bank#1 or bank#2 by
addressing the higher bank address, $8000 - $FFFF, to fetch
data.
5.2. Map of Memory and I/Os
*NMI SOURCE:
*INT SOURCE:
*I/O PORT:
―
INT1 ( from TIMER 1 )
H/W registers , I/Os
$00000
* MEMORY MAP
WORKING SRAM(192 bytes)
$0003F
$00040
SRAM for STACK and
Data Storage (304bytes)
SUNPLUS TEST PROGRAM
$000FF
$00100
ROM BANK #1
$0022F
$00300
$00400
ROM BANK #2
UNUSED
USER's PROGRAM
DATA AREA
ROM BANK
LCD Buffer ( 80 bytes)
$0037F
$007FF
$00800
$07FFF
$08000
$0FFFF
$10000
$13FFF
$14000
$17FFF
―
I/O AB_CTRL $0001
―
PORT IOAB $0002
―
PORT IOEF $0004
―
PORT IOCD $0003
―
I/O CD_CTRL $0000
―
I/O EF_CTRL $0006
―
INT0 ( from TIMER 0 )
―
INT1 ( from TIMER 1 )
―
2 KHz
―
T2 Hz ( 2Hz / 1 Hz)
―
T16 Hz ( 4Hz/8Hz/16Hz/32Hz )
―
128 Hz
―
EXT INT ( from IOCD0 pin )
―
UART
Note:
$7FFA - $7FFF in ROM bank#0, and $FFFA - $FFFF in bank#1 - 2
are reserved for reset vectors.
$7FF2 - $7FF7 in bank#0, and $FFF2 - $FFF7 in bank#1 - 2 are
reserved for testing.
5.3. Operating States
The SPL61A supports three operating states: standby, halt, and
operating. Following table shows the differences between the
three operating states.
Operating
Halt
Standby
CPU
ON
OFF
OFF
32768 oscillator
ON
ON
OFF
LCD driver
ON
ON/OFF
OFF
In operating state, all modules (CPU, 32768 oscillator,
timer/counter, LCD driver…) are activated. The halt/standby
state is entered by writing to SLEEP register ($09). There are
four wake-up sources in SPL61A: port IOEF wake-up, TIMR0
wake-up, 4Hz/8Hz/16Hz/32Hz wake-up and 2Hz/1Hz wake-up. If
any wake-up event occurs, execution of the next instruction
continues in the operating state.
When in standby, all modules will be shut down, and RAM and
I/Os remain in their previous states. The current consumption is
minimized in standby. By writing to SLEEP register but keeps
32768 oscillator running, the system is in halt state. In halt state,
CPU clock is halted while it waits for an event (key press, timer
overflow) to generate a wake-up. The 32768 related modules
(timer/counter, LCD driver…) may remain active in the halt state.
Following figure is a state diagram for the SPL61A.
HALT
OPERATING
STANDBY
Write to SLEEP register,
32768 oscillator OFF
Wake-up or user reset
WieoSEPrgse,
Wk-po srrst
State Diagram of SPL61A
5.4. Speech and Melody
Since SPL61A provides large ROM and wide range of CPU
operating speed, it is the most appropriate IC for speech and
melody synthesis. For speech synthesis, SPL61A provides
several timer interrupts for precise sampling frequency. Users
can record or synthesize the sound and digitize it into the ROM.
The sound then can be played back in the sequence assigned by
users’ programs. Several algorithms are recommended for high
fidelity and good compression of sound: such as PCM and
ADPCM.
For melody synthesis, SPL61A provides the dual tone mode.
Once in the dual tone mode, users only need to program the tone
frequency of each channel by writing to timer/counter TM0 and
TM1, and set the envelope of each channel. The hardware will
toggle the tone wave automatically without users’ care.
Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
AUG. 13, 2001
Version: 1.2
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