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参数资料
| 型号： | SPT8000SIT |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封装： | PLASTIC, TQFP-44 |
| 文件页数： | 10/11页 |
| 文件大小： | 130K |
| 代理商： | SPT8000SIT |
8
10/12/01
SPT8000
EQUVALENT INPUT CIRCUIT
Figure 3 shows a simplified, equivalent input circuit when
the input is being sampled. The inputs, VIN+ and VIN–,
drive the bottom plates of the sampling capacitors, CS+
and CS–, respectively. The top plates of the sampling ca-
pacitors are shorted to CM through sampling switches
SWS+ and SWS–. A sampling of the input is accom-
plished by simultaneously opening SWS+ and SWS–. An
internal clock driver circuit generates this control signal so
that the sampling instance is defined at the rising edge of
CLK input.
The SPT8000 incorporates two switches that connect VIN+
and VIN– to CM during calibration. These switches are
shown as SWC+ and SWC– in Figure 3. The typical on-
resistance of the switches is about 900
each. This con-
figuration enables the internal calibration to calibrate out
the offset error of SHA and to achieve the superb specifi-
cation for mid-scale error of the ADC. The user must en-
sure that both VIN+ and VIN– are left open or driven to CM
during calibration.
TYPICAL INTERFACE CIRCUIT
Figure 5 shows a typical interface circuit reflecting the
grounding and bypassing scheme used in the evaluation
board. All bypass capacitors must be located as close to
the package pins as possible. It is also important to keep a
minimum lead distance between the input pins, VIN+ and
VIN–, and the transformer.
It is recommended that the user follow the timing require-
ments for RESETB and CAL indicated in Figure 4. In this
example, RESETB stays logic low for two full clock cycles.
CAL must remain logic high for two or more clock cycles,
and the time from RESETB returning high to the rising
edge of CAL must be at least two clock cycles, based on
the internal operation of the SPT8000. It has been verified
that the timing specified in Figure 4 functions properly with
the evaluation board. However, it should be noted that this
time between RESETB going high and CAL going high
Figure 3 – Equivalent Input Circuit
VIN+
VIN
CM
SWC+
SWC
SWP
SWP+
SWS+
SWS
CS+
CS
8 pF
also depends on the external system design and configu-
ration. Once RESETB goes low for two clock cycles, the
SPT8000 initializes its internal bias condition. The internal
initialization takes place instantaneously. However, the
amount of time it takes for the voltages at VRT, VRC, CM,
VBS, and VREF/EXTB, to stabilize will vary depending on
the external bypassing circuits at these pins. The user
must ensure that the SPT8000 has reached a stable
operation condition before initiating a calibration by driving
CAL high. It is also a user’s responsibility to make sure that
all the power supplies have reached a stable condition
before initiating the Reset/Cal sequence.
As in the case with any high-speed, high-resolution ADCs,
the quality of clock input to the SPT8000 significantly
affects its performance. A SHA with a sample clock jitter of
tJ, sampling a full-scale input of frequency IN, has the
SNR due only to the clock jitter given by:
SNR = –20 log10(2π IN tJ)
For a 10 MHz input with a 3 ps clock jitter, SNR is limited
to 74.5 dB. It is therefore extremely important to drive the
device with a clock signal having the lowest possible jitter.
CLK
CAL
Reset/Cal
RESETB
2 clock cycles minimum
Figure 4 – Reset/Cal Timing
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