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参数资料
| 型号： | SPT8000SIT |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封装： | PLASTIC, TQFP-44 |
| 文件页数： | 9/11页 |
| 文件大小： | 130K |
| 代理商： | SPT8000SIT |
7
10/12/01
SPT8000
process warrants the required accuracy of stage 4 and
stage 5 without calibration.
The calibration sequence starts with the ADC made of
stage 4 and 5 measuring errors in MDAC3 and storing the
digital representation of each of the errors (calibration co-
efficient) in RAM. The stage 3 calibration coefficients are
used to make the ADC composed of stage 3, 4 and 5 ac-
curate to its required specifications. The next sequence
measures errors in MDAC2 by the ADC made of stages 3,
4 and 5, and stores the calibration coefficients in RAM.
This is repeated until all relevant errors of SHA and
MDACs are measured and stored in RAM.
The user can initiate the calibration by driving the CAL pin
high for more than two falling edges of CLK while holding
RESETB high. The internal microcontroller then outputs
high to the BUSY pin, indicating that the SPT8000 is in
calibration mode. BUSY will remain high until all the cali-
bration coefficients have been successfully measured and
stored in RAM. Once BUSY returns to low, the SPT8000
is ready for normal conversions of analog input at VIN+
and VIN–. The number of clock cycles it takes to complete
the digital calibration is about 1.49 million, which trans-
lates to 74.5 ms for a 20 MHz clock. By driving low the
asynchronous reset pin, RESETB, the user can interrupt
the calibration in progress. When the SPT8000 detects
RESETB low, it clears all the calibration coefficients in
RAM and sits in the initial idle state. In order to start new
conversions to the specifications, the user must drive
RESETB high again and drive CAL high to restart
calibration.
It is important to note that both VIN+ and VIN– pins are
shorted to CM through a pair of internal switches. There-
fore, the user must either leave VIN+ and VIN– open or
drive both to CM during the calibration mode. The digital
ouputs during the calibration are controlled by the internal
calibration machine and should be disregarded. It is the
user’s responsibility to establish stable power supplies
and references (when external references are used) prior
to issuing CAL high, and to maintain their integrity during
the calibration.
POWER-ON SEQUENCE AND
INITIALIZATION
Power supplies AVDD and OVDD may be turned on in any
sequence. Inputs VIN+, VIN–, and CLK may be driven only
after all the supplies have been established. If external ref-
erences are used to drive VRT and VRC pins, they can be
applied only after all supplies are in their normal range.
Once all supplies have been provided, CLK input may be
driven with a frequency up to 20 MHz. The user must then
initialize the SPT8000 in order to obtain the specified per-
formance. To do this, the user must first drive RESETB pin
to logic low for at least one full clock cycle and subse-
quently drive CAL high to initiate the internal calibration
(see Internal Digital Calibration and Typical Interface Cir-
cuit sections).
REFERENCE CIRCUIT
Figure 2, Equivalent Reference Circuit, shows the equiva-
lent circuit that produces VRT, VRC, CM and VREF/EXTB.
The on-chip bandgap circuit creates temperature-stable
reference voltages of 2.25 V and 1.0 V. The op amp A1
provides a buffer for 2.25 V and drives the CM pin, as well
as the internal ADC core circuitry. The 1.0 V output from
the bandgap has about 4.7 k
output impedance to the
VREF/EXTB pin. The span of the ADC is set to +VREF and
–VREF about CM as shown in Figure 2, where VREF is the
voltage at pin VREF/EXTB. A2 and A3 provide low imped-
ance outputs at VRT and VRC. It should be noted that all
three op amps in figure 2 (A1, A2, and A3) require an ex-
ternal capacitor of 4.7 F or larger from each output pin
(VRT, VRC, or CM) to AGND for compensation as well as
noise reduction.
The finite output impedance of the VREF/RSTB pin allows
the user to use an external reference circuit to overdrive
this pin. The user may do so in order to set a different ADC
span voltage or to obtain a span voltage that has less drift
over temperature than the internal reference. Note that the
specified performance is guaranteed only for VREF=1.0 V.
The user can also drive VRT and VRC directly with external
buffers by shorting the VREF/RSTB pin to AGND exter-
nally. The internal comparator COMP detects this and
disables both A2 and A3, making VRT and VRC pins high
impedance.
Bandgap &
Reference
Generator
+
+
+
+
COMP
A1
A3
A2
To ADC Core
AGND
VREF
R
VREF
4.7 kW
0.25 V
1.0 V
2.25 V
R
VREF
R
AVDD
VRT
CM
2.25 V
VREF/EXTB
VRC
Figure 2 – Equivalent Reference Circuit
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