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参数资料
| 型号： | SPT8100 |
| 厂商： | Fairchild Semiconductor Corporation |
| 英文描述： | 16-BIT, 5 MSPS CMOS A/D CONVERTER |
| 中文描述： | 16位，5 MSPS的的CMOS A / D转换 |
| 文件页数： | 2/10页 |
| 文件大小： | 91K |
| 代理商： | SPT8100 |
2
1/9/02
SPT8100
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25 °C
Supply Voltages
AV
DD
...................................................................... +6 V
DV
DD
..................................................................... +6 V
OV
DD
..................................................................... +6 V
Input Voltages
Analog Input .................................
–
0.5 V to V
DD
+0.5 V
CLK Input ............................................................... V
DD
AV
DD
–
DV
DD
.................................................. ±100 mV
Delta between AGND, DGND, and OGND...... ±100 mV
Output
Digital Outputs.................................................... 10 mA
Temperature
Operating Temperature...........................
–
40 to +85
°
C
Junction Temperature ...................................... +175
°
C
Lead Temperature (soldering 10 seconds) ...... +300
°
C
Storage Temperature ............................
–
65 to +150
°
C
Note 1: Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions in
typical applications.
ELECTRICAL SPECIFICATIONS
T
A
=T
MIN
to T
MAX
, AV
DD
=DV
DD
=+5.0 V, OV
DD
= 3.3 V,
S
=5 MSPS, 2.5 V
PP
input span, Gain=0 dB, R
EXT
=1.43 k
, unless
otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT8100
TYP
PARAMETERS
MIN
MAX
UNITS
Resolution
15.9
16
Bits
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
Gain Error
1
Offset Error
2
V
V
IV
IV
±1.25
±0.5
LSB
LSB
%FSR
%FSR
–
7.5
–
5
+7.5
+5
Analog Input (into PGA)
Differential Input Voltage Range
V
IN
+, V
IN
–
Input Capacitance
Input Resistance
3
Input Bandwidth
4
Input Common Mode Voltage Range
V
IV
IV
V
V
5
V
PPD
pF
k
MHz
V
15
PGA Gain = 0 dB
PGA Gain = 0 dB
5.5
12
2.40
1.15
3.65
Programmable Gain Amp
Composite Input-Referred
Noise Floor
IN
> 300 kHz
PGA Gain = 0 dB
PGA Gain = 2.9 dB
PGA Gain = 5.8 dB
PGA Gain = 11.8 dB
PGA Gain = 14.8 dB
PGA Gain = 17.5 dB
PGA Gain = 19.5 dB
V
V
V
V
V
V
V
V
VI
VI
1.4
1.5
1.6
2.0
2.3
2.6
2.8
19.5
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
LSB
RMS
dB
dB
dB
PGA Range
PGA Gain Steps
3
PGA Gain Accuracy
0,2.9,5.8,11.8,14.8,17.5,19.5
±0.3
Conversion Characteristics
Maximum Conversion Rate
Pipeline Delay (Latency)
5
Reset Pulse Time (
RS
)
Reset Calibration Time
VI
IV
IV
V
5
MSPS
Clocks
Clocks
ms
5.5
3
FS = 5 MSPS
150
References and External Bias
V
RT
–
V
RB
(Internal Ref)
Bias Resistor Range (External)
V
CM
Output Voltage
V
CM
Output Current
V
RT
V
RB
VI
V
IV
IV
V
V
2.375
800
2.275
2.5
1430
2.40
2.625
2500
2.525
47
3.85
1.35
V
V
μA
V
V
3.45
0.95
3.65
1.15
1
Total gain error of PGA and ADC using internal references.
2
Total offset error of PGA and ADC relative to mid-scale.
3
See table I for input resistance as a function of PGA gain.
4
Input bandwidth is a frequency to which the fundamental energy drops by 3 dB
5
The input is sampled on the falling edge of the clock and is available on the
output after the rising edge of the clock, 5.5 clock cycles later.
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