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参数资料
| 型号： | SPT8100SIT |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 16-BIT, 5 MSPS CMOS A/D CONVERTER |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44 |
| 封装： | PLASTIC, LQFP-44 |
| 文件页数： | 8/10页 |
| 文件大小： | 91K |
| 代理商： | SPT8100SIT |
8
1/9/02
SPT8100
Figure 5
–
Timing Diagram 2
CLK
Digital
Outputs
OE
t
D1
t
D2
t
D3
Table II
–
Timing Parameters
Parameter
CLK high to Data Valid
OE inactive to HiZ
OE active to Data Valid
Symbol
t
D1
t
D2
t
D3
Min
18
10
10
Typ Max
24
16
16
Units
ns
ns
ns
40
1
30
30
1
Conditions: load capacitance = 20 pF, V
OH
= 3.3 V
FFT Plot
Typical Differential Linearity Error (DLE)
Test Conditions:
IN
= 2 MHz
CLK
= 4.4 MHz
PGA Gain = 18 dB
R
EXT
= 1.08 k
ADC Input (Post PGA) =
–
5.4 dBFS
T
A
= +25
°
C
Test Conditions:
IN
= 75 kHz
CLK
= 4.4 MHz
PGA Gain = 0 dB
Near Full-Scale Input
Two-Tone Intermodulation FFT
Spurious-Free Dynamic Range
100
95
90
85
80
75
70
65
60
55
50
45
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
0
5 V
P-P
0.9 MHz, low
0.9 MHz, high
0.9 MHz, med
2 MHz, high
2 MHz, med
2 MHz, low
3 MHz, high
3 MHz, med
3 MHz, low
S
Composite Level at ADC Input (dBFS)
Test Conditions:
1
= 890 kHz
2
= 900 kHz
CLK
= 4.4 MHz
PGA Gain = 6 dB
R
EXT
= 1.43 k
ADC Input (Post PGA) =
–
8.0 dBFS
T
A
= +25
°
C
Test Conditions:
10 MSPS, 5 V, 25
°
C
Low: R
EXT
=1.43 k
@96 mA
Med: R
EXT
=1.24 k
@109 mA
High: R
EXT
=1 k
@129 mA
D
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