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参数资料
| 型号： | SSD1812Z |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller CMOS |
| 中文描述： | LCD段/与普通的CMOS驱动器控制器 |
| 文件页数： | 14/28页 |
| 文件大小： | 434K |
| 代理商： | SSD1812Z |
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SSD1812
14
REV 1.2
12/99
S OLOMON
M/S
This pin is master/slave mode selection input. When this pin is pulled
high, master mode is selected and CL, M, MSTAT and DOF will be output
to slave devices. When pulled low, slave mode is selected. CL, M, DOF are
required to be input from master device while MSTAT is high impedance.
M
This pin is the frame signal input/output. In master mode, the pin supplies
frame signal to slave devices while in slave mode, the pin receives frame
signal from the master device.
MSTAT
This pin is used together with M in master operation for static drive out-
put. It becomes high impedance in slave mode operation.
CL
This pin is the display clock input/output. In master mode, the pin sup-
plies display clock signal to slave devices while in slave mode, the pin
receives display clock signal from the master device.
DOF
This pin is LCD blanking control input/output. In master mode, the pin
supplies on/off signal to slave devices. In slave mode, the pin receives on/
off signal from the master device.
CLS
This pin is a internal clock enable input pin. When this pin is high, the
internal clock is enabled. The internal clock will be disabled when it is low,
an external clock should be input to CL pin.
RES
This pin is reset signal input. When the pin is low, initialization of the chip
is executed.
P/S
This pin is serial/parallel interface select input. When P/S is high, parallel
mode is selected and when P/S is low, serial mode is selected. In serial
mode, only write operation is allowed.
CS1
,
CS2
These pin are chip select inputs. The chip is enabled for data operation
only when CS1 is low and CS2 is high.
C68/80
This pin is microprocessor interface select input. When the pin is high,
6800 series interface is selected and when the pin is low, 8080 series inter-
face is selected.
D
0
-D
7
These pins are 8-bit bi-directional data bus to be connected to the micro-
processor’s data bus. When serial mode is selected, D
7
is the serial data
input SDA and D
6
is the serial clock input SCK.
D/C
This pin is control/display data input control flag. When the pin is high,
the data on D
0
-D
7
is display data. When the pin is low, the data on D
0
-D
7
is
control data.
R/W(WR)
This pin is microprocessor interface signal. When interfacing to an 6800-
series microprocessor, the signal indicates read mode when high and write
mode when low. When interfacing to an 8080-microprocessor, a data write
operation is initiated when R/W(WR) is low and the chip is selected.
E(RD)
This pin is microprocessor interface signal. When interfacing to an 6800-
series microprocessor, a data operation is initiated when E(RD) is high and
the chip is selected. When interfacing to an 8080-microprocessor, a data
read operation is initiated when E(RD) is low and the chip is selected.
V
DD
Power supply pin.
V
SS
Ground.
V
SS1
Reference voltage input for internal DC-DC converter. The voltage of
generated VEE equals to the multiple factor (2X, 3X or 4X) times the pro-
tential different between this pin,
V
SS1
, and
V
DD
. All generated voltage is
referenced to
V
DD
.
Note: voltage at this input pin must less than or equal to
V
SS
.
V
EE
This is the most negative voltage supply pin of the chip. It can be sup-
plied externally or generated by the internal DC-DC converter.
When using internal DC-DC converter as generator, voltage at this pin
is for internal reference only. It CANNOT be used for driving external cir-
cuitries.
C
3N
, C
1P
, C
1N
, C
2P
and C
2N
When internal DC-DC voltage converter is used, external capacitor(s)
is/are connected among these pins.
V
L6
This pin is the most negative LCD driving voltage. It can be supplied
externally or generated by the internal regulator.
V
F
This pin is an input of the internal voltage regulator. When internal regu-
lator is used to generate V
L6
, external resistors are connected between
V
DD
and V
F
, and V
F
and V
L6
, respectively (see application circuit).
V
FS
This pin is an input to provide an external voltage reference for the
internal voltage regulator. It is only enabled in External Input chip options.
IRS
This pin is an input pin to enable the internal resistors network for the
voltage regulator when IRS is high. When it is low, the external resistors
R1/R2 should be connected to VL6 and VF.
HPM
This pin is an input pin to enable the high power current mode when it is
low. The contrast curves in High Power Mode will be different to Normal
Mode. Details of the High Power Mode Contrast curve is TBD.
V
L2
, V
L3
, V
L4
and V
L5
(Voltages referenced to V
DD
)
LCD driving voltages. They can be supplied externally or generated by
the internal smart bias divider. They have the following relationship:
V
DD
> V
L2
> V
L3
> V
L4
> V
L5
> V
L6
ROW0 - ROW63
These pins provide the row driving signal COM0 - COM53 to the LCD
panel. See Table.1 about the COM signal mapping in different multiplex
ratio N.
ICONS
This pin is the special icons line.
SEG0 - SEG131
These pins provide the LCD column driving signal. Their voltage level is
V
DD
during sleep mode and standby mode.
1:6 bias
1:8 bias
V
L2
V
L3
V
L4
V
L5
1/6*V
L6
2/6*V
L6
4/6*V
L6
5/6*V
L6
1/8*V
L6
2/8*V
L6
6/8*V
L6
7/8*V
L6
PIN DESCRIPTIONS
相关PDF资料 |
PDF描述 |
|---|---|
| SSD1815 | SEMICONDUCTOR TECHNICAL DATA |
| SSD1815T1R | SEMICONDUCTOR TECHNICAL DATA |
| SSD1815T2R | SEMICONDUCTOR TECHNICAL DATA |
| SSD1815T3R | SEMICONDUCTOR TECHNICAL DATA |
| SSD1815TR | SEMICONDUCTOR TECHNICAL DATA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SSD1815 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SEMICONDUCTOR TECHNICAL DATA |
| SSD1815B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1815BT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1815BT2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LCD Segment / Common Driver with Controller |
| SSD1815BZ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LCD Segment / Common Driver with Controller |
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