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参数资料
| 型号： | SSD1812Z |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LCD Segment / Common Driver with Controller CMOS |
| 中文描述： | LCD段/与普通的CMOS驱动器控制器 |
| 文件页数： | 17/28页 |
| 文件大小： | 434K |
| 代理商： | SSD1812Z |
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S OLOMON
SSD1812
17
REV 1.2
12/99
Oscillation Circuit
enable
OSC1
OSC2
Internal pwell resistor
Oscillator enable
Buffer
enable
(CLS)
(CL)
Figure 6. Oscillator Circuitry
LCD Driving Voltage Generator and Regulator
This module generates the LCD voltage needed for display output.
It takes a single supply input and generate necessary bias voltages.
It consists of:
1. 2X, 3X and 4X DC-DC voltage converter
Please refer to application notes.
2. Voltage Regulator (Voltages referenced to V
DD
)
Feedback gain control for initial LCD voltage. External resistors
are connected between V
DD
and V
F
, and between V
F
and V
L6
.
These resistors are chosen to give the desired V
L6
according to
the following equation:
V
L6
= (1 + R
2
/R
1
)V
ref
where Vref is the internally generated reference voltage with a
known R
1
and R
2
, and V
ref
can be calculated by a measured V
L6
.
R
1
and R
2
are the resistance values of the resistors between V
DD
and V
F
, and V
F
and V
L6
, respectively.
3. Smart Bias Divider
Divide the regulator output to give the LCD driving voltages (V
L2
-
V
L5
). This is a low power consumption circuit which saves most of
the display current.
4. Contrast Control (Voltages referenced to V
DD
)
Software control of 64 voltage levels of LCD voltage.
5. Bias Ratio Selection circuitry
Software control of 1/6 and 1/8 bias ratio to match the characteris-
tic of LCD panel. In addition, 1/4, 1/5, 1/7 and 1/9 bias ratios are
software selectable for any mux application.
6. Self adjust temperature compensation circuitry
Provide 8 different compensation grade selections to satisfy the
various liquid crystal temperature grades. The grading can be
selected by software control. Defaulted temperature coefficient
(TC) value is -0.05%/
o
C.
187 Bit Latch
A register carries the display signal information. In 132 X 55 display
mode. Data will be fed to the HV-buffer Cell and level-shifted to the
required level.
Level Selector
Level Selector is a control of the display synchronization. Display
voltage can be separated into two sets and used with different
cycles. Synchronization is important since it selects the required LCD
voltage level to the HV Buffer Cell, which in turn outputs the COM or
SEG LCD waveform.
HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter which translates the low
voltage output signal to the required driving voltage. The output is
shifted out with an internal FRM clock which comes from the Display
Timing Generator. The voltage levels are given by the level selector
which is synchronized with the internal M signal.
Reset Circuit
When RES input is low, the chip is initialized with the following sta-
tus:
1. Display is OFF
2. 132x48 [Not included ICONS line] Display Mode
3. Normal segment and display data column address mapping
(SEG0 mapped to address 00H)
4. Read-modify-write mode is OFF
5. Power control register is set at 000B.
6. Shift register data clear in serial interface
7. Bias ratio is set at 1/8
8. Static indicator is OFF
9. Display start line is set at display RAM address 0
10. Column address counter is set at 0
11. Page address is set at 0
12. Normal scan direction of the COM outputs
13. Internal Regulator Resistor Ratio at 4
14. Contrast control register is set at 20H
15. Test mode is OFF
16. Temperature Coefficient is set to PTC0
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry
(Figure 6). The oscillator generates the clock for the DC-DC voltage
converter. This clock is also used in the Display Timing Generator.
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