参数资料
型号: SST25LF020A-33-4I-SAE-T
厂商: Microchip Technology
文件页数: 10/27页
文件大小: 0K
描述: IC FLASH SER 2MB 33HZ SPI 8SOIC
标准包装: 2,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 2M (256K x 8)
速度: 33MHz
接口: SPI 串行
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
2 Mbit SPI Serial Flash
A Microchip Technology Company
SST25LF020A
Not Recommended for New Designs
7. Block addresses for: use A MS -A 15 , remaining addresses can be V IL or V IH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
11. Manufacturer’s ID is read with A 0 =0, and Device ID is read with A 0 =1. All other address bits are 00H. The Manufacturer
and Device ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 43H for SST25LF020A
Read (20 MHz)
The Read instruction supports up to 20 MHz, it outputs the data starting from the specified address
location. The data output stream is continuous through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will automatically increment until the highest memory
address is reached. Once the highest memory address is reached, the address pointer will automati-
cally increment to the beginning (wrap-around) of the address space, i.e. for 2 Mbit density, once the
data from address location 3FFFFH had been read, the next output will be from address location
00000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A 23 -
A 0 ]. CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read
sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI
03
ADD.
ADD.
ADD.
SO
MSB
MSB
HIGH IMPEDANCE
N
D OUT
N+1
D OUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
MSB
1242 F04.0
Figure 5: Read Sequence
?2011 Silicon Storage Technology, Inc.
10
DS25080A
11/11
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