参数资料
型号: SST89E58RD2-40-C-PIE
厂商: SILICON STORAGE TECHNOLOGY INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封装: LEAD FREE, PLASTIC, MS-011AC, DIP-40
文件页数: 33/91页
文件大小: 1017K
代理商: SST89E58RD2-40-C-PIE
Preliminary Specifications
FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
39
2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
X = Don’t care
4.2 In-Application Programming Mode
The device offers either 16/24/40/72 KByte of in-application
programmable flash memory. During in-application pro-
gramming, the CPU of the microcontroller enters IAP
mode. The two blocks of flash memory allow the CPU to
execute user code from one block, while the other is being
erased or reprogrammed concurrently. The CPU may also
fetch code from an external memory while all internal flash
is being reprogrammed. The mailbox registers (SFST,
SFCM, SFAL, SFAH, SFDT and SFCF) located in the spe-
cial function register (SFR), control and monitor the
device’s erase and program process.
Table 4-6 and Table 4-7 outline the commands and their
associated mailbox register settings.
4.2.1 In-Application Programming Mode Clock
Source
During IAP mode, both the CPU core and the flash control-
ler unit are driven off the external clock. However, an inter-
nal oscillator will provide timing references for Program and
Erase operations. The internal oscillator is only turned on
when required, and is turned off as soon as the flash oper-
ation is completed.
4.2.2 Memory Bank Selection for In-Application
Programming Mode
With the addressing range limited to 16 bit, only 64 KByte
of program address space is “visible” at any one time. As
shown in Table 4-5, the bank selection (the configuration of
EA# and SFCF[1:0]), allows Block 1 memory to be overlaid
on the lowest 8 KByte of Block 0 memory, making Block 1
reachable. The same concept is employed to allow both
Block 0 and Block 1 flash to be accessible to IAP opera-
tions. Code from a block that is not visible may not be used
as a source to program another address. However, a block
that is not “visible” may be programmed by code from the
other block through mailbox registers.
The device allows IAP code in one block of memory to pro-
gram the other block of memory, but may not program any
location in the same block. If an IAP operation originates
physically from Block 0, the target of this operation is implic-
itly defined to be in Block 1. If the IAP operation originates
physically from Block 1, then the target address is implicitly
defined to be in Block 0. If the IAP operation originates from
external program space, then, the target will depend on the
address and the state of bank selection.
4.2.3 IAP Enable Bit
The IAP enable bit, SFCF[6], enables in-application pro-
gramming mode. Until this bit is set, all flash programming
IAP commands will be ignored.
TABLE
4-4: ADDITIONAL READ COMMANDS IN EXTERNAL HOST MODE
Address
Data
60H
X
SC1_i
SC0_i
SB1_i
SB2_i
SB3_i
61H
XXXXXX
EDC_i
X
T4-4.0 1255
TABLE
4-5: IAP ADDRESS RESOLUTION FOR SST89E/V516RD2
EA#
SFCF[1:0]
Address of IAP Inst.
Target Address
Block Being Programmed
1
00
>= 2000H (Block 0)
None1
1. No operation is performed because code from one block may not program the same originating block
1
00
>= 2000H (Block 0)
< 2000H (Block 1)
Block 1
1
00
< 2000H (Block 1)
Any (Block 0)
Block 0
1
01, 10, 11
Any (Block 0)
>= 2000H (Block 0)
None1
1
01, 10, 11
Any (Block 0)
< 2000H (Block 1)
Block 1
0
00
From external
>= 2000H (Block 0)
Block 0
0
00
From external
< 2000H (Block 1)
Block 1
0
01, 10, 11
From external
Any (Block 0)
Block 0
T4-5.0 1255
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SST89E58RD2-40-C-PIF2 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU
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