参数资料
型号: SST89V54RD2-33-C-NJE
厂商: Microchip Technology
文件页数: 12/92页
文件大小: 0K
描述: IC MCU 8BIT 24KB FLASH 44PLCC
标准包装: 26
系列: FlashFlex®
核心处理器: 8051
芯体尺寸: 8-位
速度: 33MHz
连通性: EBI/EMI,SPI,UART/USART
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 36
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
EEPROM 大小: 8K x 8
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 44-LCC
包装: 管件
2011 Silicon Storage Technology, Inc.
DS25087A
10/11
2
FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Not Recommended for New Designs
A Microchip Technology Company
Product Description
The SST89V54RD2/RD and SST89V58RD2/RD are members of the FlashFlex family of 8-bit micro-
controller products designed and manufactured with SST’s patented and proprietary SuperFlash
CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector
offer significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction
set and are pin-for-pin compatible with standard 8051 microcontroller devices.
The devices come with 24/40 KByte of on-chip flash EEPROM program memory which is partitioned
into 2 independent program memory blocks. The primary Block 0 occupies 16/32 KByte of internal pro-
gram memory space and the secondary Block 1 occupies 8 KByte of internal program memory space.
The 8-KByte secondary block can be mapped to the lowest location of the 16/32 KByte address space;
it can also be hidden from the program counter and used as an independent EEPROM-like data mem-
ory.
In addition to the 24/40 KByte of EEPROM program memory on-chip and 1024 x8 bits of on-chip RAM,
the devices can address up to 64 KByte of external program memory and up to 64 KByte of external
RAM.
The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted
with a special adapter and the firmware for SST’s devices. During power-on reset, the devices can be
configured as either a slave to an external host for source code storage or a master to an external host
for an in-application programming (IAP) operation. The devices are designed to be programmed in-
system and in-application on the printed circuit board for maximum flexibility. The devices are pre-pro-
grammed with an example of the bootstrap loader in the memory, demonstrating the initial user pro-
gram code loading or subsequent user code updating via the IAP operation. The sample bootstrap
loader is available for the user’s reference and convenience only; SST does not guarantee its function-
ality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.
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