参数资料
型号: ST16C2552CJ44TR-F
厂商: Exar Corporation
文件页数: 6/34页
文件大小: 0K
描述: IC UART FIFO 16B DUAL 44PLCC
标准包装: 500
特点: *
通道数: 2,DUART
FIFO's: 16 字节
规程: RS232,RS485
电源电压: 3.3 V ~ 5 V
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 带卷 (TR)
ST16C2552
14
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
REV. 4.2.2
2.12
Internal Loopback
The 2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 11. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
M
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dem
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Gen
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Purpo
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Contro
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In
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D
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Bus
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ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
(OP2A#/OP2B#)
VCC
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